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Searched refs:MPU_RASR_TEX_Pos (Results 1 – 25 of 359) sorted by relevance

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/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_cortex.h165 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
166 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
167 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
168 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/bsp/efm32/Libraries/emlib/src/
A Dem_mpu.c105 (init->tex << MPU_RASR_TEX_Pos) | in MPU_ConfigureRegion()
/bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/
A Dcore_cm0plus.h563 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/efm32/Libraries/CMSIS/Include/
A Dcore_cm0plus.h519 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
520 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dcore_cm0plus.h554 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
555 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/CME_M7/CMSIS/CMSIS/Include/
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32l07x/Libraries/CMSIS/CORE/
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h563 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h563 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/Core/
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/nxp/lpc/lpc43xx/Libraries/CMSIS/Include/
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/
A Dcore_sc000.h540 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
541 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_cm0plus.h522 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
523 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h551 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
552 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/nv32f100x/lib/inc/
A Dcore_cm0plus.h563 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
/bsp/xplorer4330/Libraries/CMSIS/Include/
A Dcore_sc000.h553 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …
A Dcore_cm0plus.h534 #define MPU_RASR_TEX_Pos 19 /*!< MPU … macro
535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU …

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