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Searched refs:MR (Results 1 – 25 of 38) sorted by relevance

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/bsp/rm48x50/HALCoGen/
A Dmisra-c.txt3 /*SAFETYMCUSW 26 S MR:12.3 <REVIEWED> "Infinite loops needed" */
4 /*SAFETYMCUSW 69 S MR:12.2 <REVIEWED> "pragma for interrupts a must" */
8 /*SAFETYMCUSW 440 S MR:11.3 <REVIEWED> "Casting for #defines" */
9 /*SAFETYMCUSW 5 C MR: <REVIEWED> "Infinite loops needed" */
10 /*SAFETYMCUSW 28 D MR: <REVIEWED> "Infinite loops needed" */
14 /*SAFETYMCUSW 189 S MR: <REVIEWED> "Input lines may exceed" */
15 /*SAFETYMCUSW 62 D MR:16.7 <REVIEWED> "Pointer parameters to be const" */
22 /*SAFETYMCUSW 488 S MR:10.1 <REVIEWED> "Cannot avoid multiple OR�ing" */
28 /*SAFETYMCUSW 88 S MR:2.1 <REVIEWED> "Assembly in C" */
43 /*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
[all …]
/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/
A Ddrv_pwm.c145 get_frequence = pwmClock / (base->MR[kCTIMER_Match_3] + 1); in lpc_drv_pwm_get()
150 …get_duty = (100*(base->MR[kCTIMER_Match_3] + 1 - base->MR[kCTIMER_Match_0]))/(base->MR[kCTIMER_Mat… in lpc_drv_pwm_get()
155 …get_duty = (100*(base->MR[kCTIMER_Match_3] + 1 - base->MR[kCTIMER_Match_1]))/(base->MR[kCTIMER_Mat… in lpc_drv_pwm_get()
160 …get_duty = (100*(base->MR[kCTIMER_Match_3] + 1 - base->MR[kCTIMER_Match_2]))/(base->MR[kCTIMER_Mat… in lpc_drv_pwm_get()
208 base->MR[kCTIMER_Match_3] = pwmPeriod; in lpc_drv_pwm_set()
213 base->MR[kCTIMER_Match_0] = pulsePeriod; in lpc_drv_pwm_set()
217 base->MR[kCTIMER_Match_1] = pulsePeriod; in lpc_drv_pwm_set()
221 base->MR[kCTIMER_Match_2] = pulsePeriod; in lpc_drv_pwm_set()
/bsp/nxp/mcx/mcxn/Libraries/drivers/
A Ddrv_pwm.c101 uint32_t new_mr = ct->MR[i] * ct->MSR[p_channel] / ct->MR[p_channel]; in mcx_pwm_period_set()
136 *period_ns = ct->MR[p_channel] * pwm->counter_period_ps / 1000; in mcx_pwm_period_get()
152 ct->MSR[channel] = ct->MR[p_channel] - pulse_ns * 1000 / pwm->counter_period_ps; in mcx_pwm_pulse_set()
158 while (ct->MR[channel] != ct->MSR[channel]) in mcx_pwm_pulse_set()
180 *pulse_ns = (ct->MR[p_channel] - ct->MR[channel]) * pwm->counter_period_ps / 1000; in mcx_pwm_pulse_get()
237 ct->MR[3] = period; in mcx_drv_pwm_set()
243 ct->MR[2] = period; in mcx_drv_pwm_set()
280 ct->MR[f_channel] = ct->MR[p_channel]; in mcx_drv_pwm_set()
/bsp/microchip/same54/bsp/hri/
A Dhri_pcc_e54.h214 ((Pcc *)hw)->MR.reg |= mask; in hri_pcc_set_MR_reg()
221 tmp = ((Pcc *)hw)->MR.reg; in hri_pcc_get_MR_reg()
229 ((Pcc *)hw)->MR.reg = data; in hri_pcc_write_MR_reg()
236 ((Pcc *)hw)->MR.reg &= ~mask; in hri_pcc_clear_MR_reg()
243 ((Pcc *)hw)->MR.reg ^= mask; in hri_pcc_toggle_MR_reg()
249 return ((Pcc *)hw)->MR.reg; in hri_pcc_read_MR_reg()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_pcc_d51.h214 ((Pcc *)hw)->MR.reg |= mask; in hri_pcc_set_MR_reg()
221 tmp = ((Pcc *)hw)->MR.reg; in hri_pcc_get_MR_reg()
229 ((Pcc *)hw)->MR.reg = data; in hri_pcc_write_MR_reg()
236 ((Pcc *)hw)->MR.reg &= ~mask; in hri_pcc_clear_MR_reg()
243 ((Pcc *)hw)->MR.reg ^= mask; in hri_pcc_toggle_MR_reg()
249 return ((Pcc *)hw)->MR.reg; in hri_pcc_read_MR_reg()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_pcc_d51.h214 ((Pcc *)hw)->MR.reg |= mask; in hri_pcc_set_MR_reg()
221 tmp = ((Pcc *)hw)->MR.reg; in hri_pcc_get_MR_reg()
229 ((Pcc *)hw)->MR.reg = data; in hri_pcc_write_MR_reg()
236 ((Pcc *)hw)->MR.reg &= ~mask; in hri_pcc_clear_MR_reg()
243 ((Pcc *)hw)->MR.reg ^= mask; in hri_pcc_toggle_MR_reg()
249 return ((Pcc *)hw)->MR.reg; in hri_pcc_read_MR_reg()
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_rcm.h360 return (bool)(base->MR & RCM_MR_EZP_MS_MASK); in RCM_GetEasyPortModePinStatus()
375 return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); in RCM_GetBootRomSource()
387 base->MR |= RCM_MR_BOOTROM_MASK; in RCM_ClearBootRomSource()
/bsp/zynqmp-r5-axu4ev/drivers/
A Ddrv_uart.c117 ModeReg = pdev->uart->MR; in XUartPsSetBandRate()
169 mr = uart->MR & ~(UART_MR_CHARLEN_MASK | in uart_configure()
198 uart->MR = mr; in uart_configure()
A Ddrv_uart.h18 volatile uint32_t MR; /**< Mode Register */ member
/bsp/at91/at91sam9260/drivers/
A Dboard.c146 volatile rt_uint32_t MR; member
217 DBGU->MR = mode; in rt_hw_console_init()
A Dusart.c23 volatile rt_uint32_t MR; member
150 uart->port->MR = mode; in at91_usart_configure()
/bsp/microchip/same54/bsp/include/component/
A Dpcc.h237 __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dpcc.h237 __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dpcc.h237 __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */ member
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_msmc.h625 return base->MR; in SMC_GetBootOptionConfig()
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/
A Dapm32f10x_eth.c477 ETH->ADDR_B.MR = reg; in ETH_ReadPHYRegister()
516 ETH->ADDR_B.MR = reg; in ETH_WritePHYRegister()
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/
A Dapm32f4xx_eth.c502 ETH->ADDR_B.MR = reg; in ETH_ReadPHYRegister()
540 ETH->ADDR_B.MR = reg; in ETH_WritePHYRegister()
/bsp/hpmicro/hpm6800evk/board/
A Dboard.c988 HPM_DDRPHY->MR = (3UL << 0) /* BL = 3 */ in init_ddr2_800()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_ddrphy_regs.h36 __RW uint32_t MR; /* 0x54: */ member
/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/
A Dapm32f10x.h6210 __IOM uint32_t MR : 5; member
/bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Include/
A Dapm32f4xx.h5687 __IOM uint32_t MR : 5; member
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA4M2AD.h370 … __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register member
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA4E2B9.h352 …__IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting … member
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6E2BB.h352 …__IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting … member
/bsp/frdm-k64f/device/
A DMK64F12.h9033 __I uint8_t MR; /**< Mode Register, offset: 0x7 */ member

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