1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _DMA_REGS_H_ 41 #define _DMA_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup dma 79 * @defgroup dma_registers DMA_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 81 * @details DMA Controller Fully programmable, chaining capable DMA channels. 82 */ 83 84 /** 85 * @ingroup dma_registers 86 * Structure type to access the DMA Registers. 87 */ 88 typedef struct { 89 __IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */ 90 __IO uint32_t st; /**< <tt>\b 0x104:</tt> DMA ST Register */ 91 __IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */ 92 __IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */ 93 __IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */ 94 __IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */ 95 __IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */ 96 __IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */ 97 } mxc_dma_ch_regs_t; 98 99 typedef struct { 100 __IO uint32_t cn; /**< <tt>\b 0x000:</tt> DMA CN Register */ 101 __I uint32_t intr; /**< <tt>\b 0x004:</tt> DMA INTR Register */ 102 __R uint32_t rsv_0x8_0xff[62]; 103 __IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 104 } mxc_dma_regs_t; 105 106 /* Register offsets for module DMA */ 107 /** 108 * @ingroup dma_registers 109 * @defgroup DMA_Register_Offsets Register Offsets 110 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 111 * @{ 112 */ 113 #define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 114 #define MXC_R_DMA_ST ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ 115 #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ 116 #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ 117 #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ 118 #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ 119 #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ 120 #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ 121 #define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 122 #define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 123 #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 124 /**@} end of group dma_registers */ 125 126 /** 127 * @ingroup dma_registers 128 * @defgroup DMA_CN DMA_CN 129 * @brief DMA Control Register. 130 * @{ 131 */ 132 #define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */ 133 #define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */ 134 #define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */ 135 #define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */ 136 #define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */ 137 #define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */ 138 139 #define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */ 140 #define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */ 141 142 #define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */ 143 #define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */ 144 145 #define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */ 146 #define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */ 147 148 /**@} end of group DMA_CN_Register */ 149 150 /** 151 * @ingroup dma_registers 152 * @defgroup DMA_INTR DMA_INTR 153 * @brief DMA Interrupt Register. 154 * @{ 155 */ 156 #define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */ 157 #define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */ 158 #define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */ 159 #define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */ 160 #define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */ 161 #define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */ 162 163 #define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */ 164 #define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */ 165 166 #define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */ 167 #define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */ 168 169 #define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */ 170 #define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */ 171 172 /**@} end of group DMA_INTR_Register */ 173 174 /** 175 * @ingroup dma_registers 176 * @defgroup DMA_CFG DMA_CFG 177 * @brief DMA Channel Configuration Register. 178 * @{ 179 */ 180 #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ 181 #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ 182 #define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */ 183 #define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */ 184 #define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */ 185 #define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */ 186 187 #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ 188 #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ 189 #define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */ 190 #define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */ 191 #define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */ 192 #define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */ 193 194 #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ 195 #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ 196 #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ 197 #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ 198 #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ 199 #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ 200 #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ 201 #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ 202 #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ 203 #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ 204 205 #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ 206 #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ 207 #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ 208 #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ 209 #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ 210 #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ 211 #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ 212 #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ 213 #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ 214 #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ 215 #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ 216 #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ 217 #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ 218 #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ 219 #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ 220 #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ 221 #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ 222 #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ 223 #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ 224 #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ 225 #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ 226 #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ 227 #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ 228 #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ 229 #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ 230 #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ 231 #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ 232 #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ 233 234 #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ 235 #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ 236 #define MXC_V_DMA_CFG_REQWAIT_DIS ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */ 237 #define MXC_S_DMA_CFG_REQWAIT_DIS (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */ 238 #define MXC_V_DMA_CFG_REQWAIT_EN ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */ 239 #define MXC_S_DMA_CFG_REQWAIT_EN (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */ 240 241 #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ 242 #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ 243 #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ 244 #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ 245 #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ 246 #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ 247 #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ 248 #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ 249 #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ 250 #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ 251 #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ 252 #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ 253 #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ 254 #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ 255 #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ 256 #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ 257 #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ 258 #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ 259 260 #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ 261 #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ 262 #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ 263 #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ 264 #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ 265 #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ 266 #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ 267 #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ 268 #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ 269 #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ 270 271 #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ 272 #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ 273 #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ 274 #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ 275 #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ 276 #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ 277 #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ 278 #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ 279 280 #define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ 281 #define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ 282 #define MXC_V_DMA_CFG_SRCINC_DIS ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */ 283 #define MXC_S_DMA_CFG_SRCINC_DIS (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */ 284 #define MXC_V_DMA_CFG_SRCINC_EN ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */ 285 #define MXC_S_DMA_CFG_SRCINC_EN (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */ 286 287 #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ 288 #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ 289 #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ 290 #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ 291 #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ 292 #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ 293 #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ 294 #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ 295 296 #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ 297 #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ 298 #define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */ 299 #define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */ 300 #define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */ 301 #define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */ 302 303 #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ 304 #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ 305 306 #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ 307 #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ 308 #define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */ 309 #define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */ 310 #define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */ 311 #define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */ 312 313 #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ 314 #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ 315 #define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */ 316 #define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */ 317 #define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */ 318 #define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */ 319 320 /**@} end of group DMA_CFG_Register */ 321 322 /** 323 * @ingroup dma_registers 324 * @defgroup DMA_ST DMA_ST 325 * @brief DMA Channel Status Register. 326 * @{ 327 */ 328 #define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */ 329 #define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */ 330 #define MXC_V_DMA_ST_CH_ST_DIS ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */ 331 #define MXC_S_DMA_ST_CH_ST_DIS (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */ 332 #define MXC_V_DMA_ST_CH_ST_EN ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */ 333 #define MXC_S_DMA_ST_CH_ST_EN (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */ 334 335 #define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */ 336 #define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */ 337 #define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */ 338 #define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */ 339 #define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */ 340 #define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */ 341 342 #define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */ 343 #define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */ 344 #define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */ 345 #define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */ 346 #define MXC_V_DMA_ST_CTZ_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */ 347 #define MXC_S_DMA_ST_CTZ_ST_OCCURRED (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */ 348 #define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */ 349 #define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */ 350 351 #define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */ 352 #define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */ 353 #define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */ 354 #define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */ 355 #define MXC_V_DMA_ST_RLD_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */ 356 #define MXC_S_DMA_ST_RLD_ST_OCCURRED (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */ 357 #define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */ 358 #define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */ 359 360 #define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */ 361 #define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */ 362 #define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */ 363 #define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */ 364 #define MXC_V_DMA_ST_BUS_ERR_OCCURRED ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */ 365 #define MXC_S_DMA_ST_BUS_ERR_OCCURRED (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */ 366 #define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */ 367 #define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */ 368 369 #define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */ 370 #define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */ 371 #define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */ 372 #define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */ 373 #define MXC_V_DMA_ST_TO_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */ 374 #define MXC_S_DMA_ST_TO_ST_OCCURRED (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */ 375 #define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */ 376 #define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */ 377 378 /**@} end of group DMA_ST_Register */ 379 380 /** 381 * @ingroup dma_registers 382 * @defgroup DMA_SRC DMA_SRC 383 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 384 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 385 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 386 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 387 * register is reloaded with the contents of DMA_SRC_RLD. 388 * @{ 389 */ 390 #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 391 #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 392 393 /**@} end of group DMA_SRC_Register */ 394 395 /** 396 * @ingroup dma_registers 397 * @defgroup DMA_DST DMA_DST 398 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 399 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 400 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 401 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 402 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 403 * @{ 404 */ 405 #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 406 #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 407 408 /**@} end of group DMA_DST_Register */ 409 410 /** 411 * @ingroup dma_registers 412 * @defgroup DMA_CNT DMA_CNT 413 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 414 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 415 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 416 * reaches 0, a count-to-zero condition is triggered. 417 * @{ 418 */ 419 #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 420 #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 421 422 /**@} end of group DMA_CNT_Register */ 423 424 /** 425 * @ingroup dma_registers 426 * @defgroup DMA_SRC_RLD DMA_SRC_RLD 427 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 428 * upon a count-to-zero condition. 429 * @{ 430 */ 431 #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ 432 #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ 433 434 /**@} end of group DMA_SRC_RLD_Register */ 435 436 /** 437 * @ingroup dma_registers 438 * @defgroup DMA_DST_RLD DMA_DST_RLD 439 * @brief Destination Address Reload Value. The value of this register is loaded into 440 * DMA0_DST upon a count-to-zero condition. 441 * @{ 442 */ 443 #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ 444 #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ 445 446 /**@} end of group DMA_DST_RLD_Register */ 447 448 /** 449 * @ingroup dma_registers 450 * @defgroup DMA_CNT_RLD DMA_CNT_RLD 451 * @brief DMA Channel Count Reload Register. 452 * @{ 453 */ 454 #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ 455 #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ 456 457 #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ 458 #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ 459 #define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */ 460 #define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */ 461 #define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */ 462 #define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */ 463 464 /**@} end of group DMA_CNT_RLD_Register */ 465 466 #ifdef __cplusplus 467 } 468 #endif 469 470 #endif /* _DMA_REGS_H_ */ 471