Home
last modified time | relevance | path

Searched refs:Mask (Results 1 – 25 of 27) sorted by relevance

12

/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/
A Dxemacps.h600 #define XEmacPs_IntEnable(InstancePtr, Mask) \ argument
603 ((Mask) & XEMACPS_IXR_ALL_MASK));
621 #define XEmacPs_IntDisable(InstancePtr, Mask) \ argument
624 ((Mask) & XEMACPS_IXR_ALL_MASK));
642 #define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ argument
645 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
663 #define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ argument
666 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/bsp/ft2004/libraries/bsp/ft_uart/
A Dft_uart_options.c27 u32 Mask; member
51 RegValue |= OptionTable[Index].Mask; in FUart_SetOptions()
55 RegValue &= ~OptionTable[Index].Mask; in FUart_SetOptions()
78 RegValue |= OptionTable[Index].Mask; in FUart_SetSpecificOptions()
99 RegValue &= ~OptionTable[Index].Mask; in FUart_ClearSpecificOptions()
A Dft_uart_intr.c38 void FUart_SetInterruptMask(Ft_Uart *UartPtr, u32 Mask) in FUart_SetInterruptMask() argument
40 u32 TempMask = Mask; in FUart_SetInterruptMask()
A Dft_uart.h118 void FUart_SetInterruptMask(Ft_Uart *UartPtr, u32 Mask);
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_pmu.c179 uint8_t PMU_GetCrystalStatus(uint32_t Mask) in PMU_GetCrystalStatus() argument
182 assert_parameters(IS_PMU_FLAG(Mask)); in PMU_GetCrystalStatus()
184 if (PMU->STS&Mask) in PMU_GetCrystalStatus()
1116 uint8_t PMU_GetResetSource(uint32_t Mask) in PMU_GetResetSource() argument
1119 assert_parameters(PMU_RESETSRC(Mask)); in PMU_GetResetSource()
1121 if (PMU->STS & Mask) in PMU_GetResetSource()
1143 void PMU_ClearResetSource(uint32_t Mask) in PMU_ClearResetSource() argument
1146 assert_parameters(PMU_RESETSRC_CLR(Mask)); in PMU_ClearResetSource()
1148 PMU->STS = Mask; in PMU_ClearResetSource()
1173 uint8_t PMU_GetDSleepWKUSource(uint32_t Mask) in PMU_GetDSleepWKUSource() argument
[all …]
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_gpio.c182 uint32_t Mask = ~(0x03 << ((Pin & 0x0000000f) * 2)); in GPIO_ExtiConfig() local
198 GPIO->INTP_TYPE_STA[Port].INTP_TYPE = (GPIO->INTP_TYPE_STA[Port].INTP_TYPE & Mask) | Type; in GPIO_ExtiConfig()
217 uint32_t Mask = ~(0x03 << ((Pin & 0x0000000f) * 2)); in GPIO_Iomux() local
219 GPIO->ALT[Port] = (GPIO->ALT[Port] & Mask) | Function; in GPIO_Iomux()
A Dbsp_common.c284 uint32_t Mask,Pos1,Pos2; in BSP_SetBit() local
289 Mask = ~(1 << Pos2); in BSP_SetBit()
294 Data[Pos1] = (Data[Pos1] & Mask) | Value; in BSP_SetBit()
301 uint32_t Mask,Pos1,Pos2; in BSP_GetBit() local
305 Mask = (1 << Pos2); in BSP_GetBit()
306 if (Data[Pos1] & Mask) in BSP_GetBit()
319 uint32_t Mask,Pos1,Pos2; in BSP_TestBit() local
323 Mask = (1 << Pos2); in BSP_TestBit()
324 if (Data[Pos1] & Mask) in BSP_TestBit()
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/
A Dxgpiops.h237 void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
238 void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
241 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
A Dxgpiops_intr.c76 void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) in XGpioPs_IntrEnable() argument
91 XGPIOPS_INTEN_OFFSET, Mask); in XGpioPs_IntrEnable()
149 void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) in XGpioPs_IntrDisable() argument
164 XGPIOPS_INTDIS_OFFSET, Mask); in XGpioPs_IntrDisable()
373 void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) in XGpioPs_IntrClear() argument
389 XGPIOPS_INTSTS_OFFSET, Mask); in XGpioPs_IntrClear()
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/
A Dlib_pmu.h305 uint8_t PMU_GetCrystalStatus(uint32_t Mask);
349 uint8_t PMU_GetResetSource(uint32_t Mask);
350 void PMU_ClearResetSource(uint32_t Mask);
353 uint8_t PMU_GetDSleepWKUSource(uint32_t Mask);
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_gpio.c599 u32 Mask = 0, PinMode = 0; in AFIO_GPxConfig() local
608 Mask = 0; in AFIO_GPxConfig()
616 Mask |= (0xF << (index * 4)); in AFIO_GPxConfig()
620 *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; in AFIO_GPxConfig()
A Dht32f1xxxx_ckcu.c153 #define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue… argument
154 #define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) argument
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_gpio.c632 u32 Mask = 0, PinMode = 0; in AFIO_GPxConfig() local
641 Mask = 0; in AFIO_GPxConfig()
649 Mask |= (0xF << (index * 4)); in AFIO_GPxConfig()
653 *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; in AFIO_GPxConfig()
A Dht32f5xxxx_ckcu.c166 #define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue… argument
167 #define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) argument
/bsp/ti/c28x/libraries/tms320f28379d/headers/include/
A DF2837xD_can.h281 bp_32 Mask:1; // 22 Access Mask Bits member
370 bp_32 Mask:1; // 22 Access Mask Bits member
449 bp_16 Mask:1; // 0 Mask data read observation member
/bsp/nxp/lpc/lpc178x/drivers/
A Ddrv_glcd.h111 void GLCD_LoadPic (U32 X_Left, U32 Y_Up, Bmp_t * pBmp, U32 Mask);
A Ddrv_glcd.c642 void GLCD_LoadPic (unsigned long X_Left, unsigned long Y_Up, Bmp_t * pBmp, unsigned long Mask) in GLCD_LoadPic() argument
661 *(pData+j) = *pSrc++ ^ Mask; in GLCD_LoadPic()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_rtc.h1650 __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) in LL_RTC_ALMA_SetMask() argument
1652 …IFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); in LL_RTC_ALMA_SetMask()
1930 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) in LL_RTC_ALMA_SetSubSecondMask() argument
1932 MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); in LL_RTC_ALMA_SetSubSecondMask()
2018 __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) in LL_RTC_ALMB_SetMask() argument
2020 …IFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); in LL_RTC_ALMB_SetMask()
2298 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) in LL_RTC_ALMB_SetSubSecondMask() argument
2300 MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); in LL_RTC_ALMB_SetSubSecondMask()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_pmu.c193 uint8_t PMU_GetStatus(uint32_t Mask) in PMU_GetStatus() argument
196 assert_parameters(IS_PMU_FLAG(Mask)); in PMU_GetStatus()
198 if (PMU->STS&Mask) in PMU_GetStatus()
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/
A Dft32f0xx_i2c.c311 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) in I2C_OwnAddress2Config() argument
318 assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); in I2C_OwnAddress2Config()
328 (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; in I2C_OwnAddress2Config()
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/
A Dhk32f0xx_i2c.c417 void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint16_t Address, uint8_t Mask) in I2C_OwnAddress2Config() argument
424 assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); in I2C_OwnAddress2Config()
434 (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; in I2C_OwnAddress2Config()
/bsp/nxp/imx/imx6sx/cortex-a9/cpu/
A DcortexA9_gcc.S310 and r0, r0, #0x03 @ Mask off unused bits of CPU ID
313 and r1, r1, #0x0F @ Mask off unused bits of ways
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/
A Dxsdps_core.h107 void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val);
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Include/
A Dlib_pmu.h268 uint8_t PMU_GetStatus(uint32_t Mask);
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_i2c.h397 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);

Completed in 59 milliseconds

12