P3_0 (reference) in projects: bsp - OpenGrok search results

Searched refs:P3_0 (Results 1 – 10 of 10) sorted by relevance

/bsp/nxp/lpc/lpc408x/drivers/
A D	drv_sdram.c	`21 LPC_IOCON->P3_0 = (1 << 0 \| 0 << 3 \| 0 << 5 \| 1 << 9); /* D0 @ P3.0 */ in sdram_gpio_config()`
/bsp/nxp/lpc/lpc178x/drivers/
A D	sdram.c	`92 LPC_IOCON->P3_0 = (1<<0 \| 0<<3 \| 0<<5 \| 1<<9); /* D0 @ P3.0 */ in EMC_GPIO_Init()`
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/
A D	cycfg_pins.h	`251 #define CYBSP_ETH_MDIO (P3_0)`
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/config/GeneratedSource/
A D	cycfg_pins.h	`105 #define CYBSP_BT_UART_RX (P3_0)`
/bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/config/GeneratedSource/
A D	cycfg_pins.h	`122 #define CYBSP_DEBUG_UART_RX (P3_0)`
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/
A D	cycfg_pins.h	`170 #define CYBSP_BT_UART_RX (P3_0)`
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A D	cycfg_pins.h	`188 #define CYBSP_BT_UART_RX (P3_0)`
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/
A D	cycfg_pins.h	`188 #define CYBSP_BT_UART_RX (P3_0)`
/bsp/Infineon/psoc6-evaluationkit-062S2/board/
A D	Kconfig	`207 comment "Notice: P3_0 --> 24; P3_1 --> 25"`
/bsp/m16c62p/drivers/
A D	iom16c62p.h	`1675 unsigned char P3_0:1;/* Port P30 register */ member`

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