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Searched refs:PARAM (Results 1 – 23 of 23) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_nvmctrl_c21.h652 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_NVMP_bf()
661 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_NVMP_bf()
664 ((Nvmctrl *)hw)->PARAM.reg = tmp; in hri_nvmctrl_write_PARAM_NVMP_bf()
685 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_NVMP_bf()
700 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_PSZ_bf()
709 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_PSZ_bf()
712 ((Nvmctrl *)hw)->PARAM.reg = tmp; in hri_nvmctrl_write_PARAM_PSZ_bf()
733 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_PSZ_bf()
749 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_RWWEEP_bf()
758 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_RWWEEP_bf()
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/bsp/microchip/saml10/bsp/hri/
A Dhri_nvmctrl_l10.h1499 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_FLASHP_bf()
1508 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_FLASHP_bf()
1511 ((Nvmctrl *)hw)->PARAM.reg = tmp; in hri_nvmctrl_write_PARAM_FLASHP_bf()
1532 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_FLASHP_bf()
1547 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_PSZ_bf()
1556 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_PSZ_bf()
1559 ((Nvmctrl *)hw)->PARAM.reg = tmp; in hri_nvmctrl_write_PARAM_PSZ_bf()
1580 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_PSZ_bf()
1596 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_DFLASHP_bf()
1605 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_write_PARAM_DFLASHP_bf()
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/bsp/loongson/ls2kdev/drivers/
A Ddrv_spi.h34 #define PARAM 0x4 macro
A Ddrv_spi.c32 SET_SPI(PARAM, 0x40); in spi_init()
/bsp/frdm-k64f/device/MK64F12/
A Dfsl_pmc.c35 uint32_t reg = base->PARAM; in PMC_GetParam()
A Dfsl_llwu.h148 *((uint32_t *)param) = base->PARAM; in LLWU_GetParam()
A Dfsl_rcm.h244 return base->PARAM; in RCM_GetResetSourceImplementedStatus()
A Dfsl_smc.c37 uint32_t reg = base->PARAM; in SMC_GetParam()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_llwu.h125 *((uint32_t *)param) = base->PARAM; in LLWU_GetParam()
A Dfsl_lpspi.h526 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); in LPSPI_GetTxFifoSize()
536 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); in LPSPI_GetRxFifoSize()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_nvmctrl_d51.h602 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; in hri_nvmctrl_get_PARAM_SEE_bit()
607 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_get_PARAM_NVMP_bf()
612 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_read_PARAM_NVMP_bf()
617 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_get_PARAM_PSZ_bf()
622 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_read_PARAM_PSZ_bf()
628 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_reg()
635 return ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_reg()
/bsp/microchip/same54/bsp/hri/
A Dhri_nvmctrl_e54.h602 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; in hri_nvmctrl_get_PARAM_SEE_bit()
607 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_get_PARAM_NVMP_bf()
612 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_read_PARAM_NVMP_bf()
617 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_get_PARAM_PSZ_bf()
622 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_read_PARAM_PSZ_bf()
628 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_reg()
635 return ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_reg()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_nvmctrl_d51.h602 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; in hri_nvmctrl_get_PARAM_SEE_bit()
607 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_get_PARAM_NVMP_bf()
612 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; in hri_nvmctrl_read_PARAM_NVMP_bf()
617 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_get_PARAM_PSZ_bf()
622 return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; in hri_nvmctrl_read_PARAM_PSZ_bf()
628 tmp = ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_get_PARAM_reg()
635 return ((Nvmctrl *)hw)->PARAM.reg; in hri_nvmctrl_read_PARAM_reg()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/
A Dnvm.c153 _nvm_dev.page_size = (8 << nvm_module->PARAM.bit.PSZ); in nvm_set_config()
154 _nvm_dev.number_of_pages = nvm_module->PARAM.bit.NVMP; in nvm_set_config()
706 uint32_t param_reg = nvm_module->PARAM.reg; in nvm_get_parameters()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dnvmctrl.h343 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ member
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dnvmctrl.h357 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ member
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dnvmctrl.h347 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dnvmctrl.h585 __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */ member
/bsp/microchip/same54/bsp/include/component/
A Dnvmctrl.h585 __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dnvmctrl.h585 __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */ member
/bsp/microchip/saml10/bsp/include/component/
A Dnvmctrl.h670 __IO NVMCTRL_PARAM_Type PARAM; /**< Offset: 0x24 (R/W 32) NVM Parameter */ member
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/
A DRV32M1_ri5cy.h651 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
4661 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
6130 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
7381 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
8266 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
9632 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
9922 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
10217 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
11199 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
11535 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
[all …]
A DRV32M1_zero_riscy.h621 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
3931 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
5491 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
7524 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
8409 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
9775 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
10065 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
10360 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
11342 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
11678 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ member
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