1 /*""FILE COMMENT""******************************************************* 2 * System Name : BSC API for RX62Nxx 3 * File Name : r_pdl_bsc.h 4 * Version : 1.02 5 * Contents : BSC API header 6 * Customer : 7 * Model : 8 * Order : 9 * CPU : RX 10 * Compiler : RXC 11 * OS : Nothing 12 * Programmer : 13 * Note : 14 ************************************************************************ 15 * Copyright, 2011. Renesas Electronics Corporation 16 * and Renesas Solutions Corporation 17 ************************************************************************ 18 * History : 2011.04.08 19 * : Ver 1.02 20 * : CS-5 release. 21 *""FILE COMMENT END""**************************************************/ 22 23 #ifndef R_PDL_BSC_H 24 #define R_PDL_BSC_H 25 26 #include "r_pdl_common_defs_RX62Nxx.h" 27 28 /* Function prototypes */ 29 bool R_BSC_Create( 30 uint32_t, 31 uint32_t, 32 uint8_t, 33 void *, 34 uint8_t 35 ); 36 bool R_BSC_CreateArea( 37 uint8_t, 38 uint16_t, 39 uint8_t, 40 uint8_t, 41 uint8_t, 42 uint8_t, 43 uint8_t, 44 uint8_t, 45 uint8_t, 46 uint8_t, 47 uint8_t, 48 uint8_t, 49 uint8_t, 50 uint8_t, 51 uint8_t 52 ); 53 bool R_BSC_SDRAM_CreateArea( 54 uint16_t, 55 uint16_t, 56 uint8_t, 57 uint8_t, 58 uint8_t, 59 uint8_t, 60 uint8_t, 61 uint8_t, 62 uint8_t, 63 uint8_t, 64 uint8_t, 65 uint16_t 66 ); 67 bool R_BSC_Destroy( 68 uint8_t 69 ); 70 bool R_BSC_Control( 71 uint16_t 72 ); 73 bool R_BSC_GetStatus( 74 uint8_t *, 75 uint16_t *, 76 uint8_t * 77 ); 78 79 /* R_BSC_Create parameter options */ 80 /* Configuration1 (pin select control) */ 81 /* Chip select pin selection */ 82 #define PDL_BSC_CS0_A 0x00000001ul 83 #define PDL_BSC_CS0_B 0x00000002ul 84 #define PDL_BSC_CS1_A 0x00000004ul 85 #define PDL_BSC_CS1_B 0x00000008ul 86 #define PDL_BSC_CS1_C 0x00000010ul 87 #define PDL_BSC_CS2_A 0x00000020ul 88 #define PDL_BSC_CS2_B 0x00000040ul 89 #define PDL_BSC_CS2_C 0x00000080ul 90 #define PDL_BSC_CS3_A 0x00000100ul 91 #define PDL_BSC_CS3_B 0x00000200ul 92 #define PDL_BSC_CS3_C 0x00000400ul 93 #define PDL_BSC_CS4_A 0x00000800ul 94 #define PDL_BSC_CS4_B 0x00001000ul 95 #define PDL_BSC_CS4_C 0x00002000ul 96 #define PDL_BSC_CS5_A 0x00004000ul 97 #define PDL_BSC_CS5_B 0x00008000ul 98 #define PDL_BSC_CS5_C 0x00010000ul 99 #define PDL_BSC_CS6_A 0x00020000ul 100 #define PDL_BSC_CS6_B 0x00040000ul 101 #define PDL_BSC_CS6_C 0x00080000ul 102 #define PDL_BSC_CS7_A 0x00100000ul 103 #define PDL_BSC_CS7_B 0x00200000ul 104 #define PDL_BSC_CS7_C 0x00400000ul 105 106 /* Address (A23-A16) pin selection */ 107 #define PDL_BSC_A23_A16_A 0x00800000ul 108 #define PDL_BSC_A23_A16_B 0x01000000ul 109 110 /* WAIT pin selection */ 111 #define PDL_BSC_WAIT_NOT_USED 0x02000000ul 112 #define PDL_BSC_WAIT_A 0x04000000ul 113 #define PDL_BSC_WAIT_B 0x08000000ul 114 #define PDL_BSC_WAIT_C 0x10000000ul 115 #define PDL_BSC_WAIT_D 0x20000000ul 116 117 /* Configuration2 (output enable control) */ 118 /* Address output control */ 119 #define PDL_BSC_A9_A0_DISABLE 0x00000001ul 120 #define PDL_BSC_A9_A4_DISABLE 0x00000002ul 121 #define PDL_BSC_A9_A8_DISABLE 0x00000004ul 122 #define PDL_BSC_A10_DISABLE 0x00000008ul 123 #define PDL_BSC_A11_DISABLE 0x00000010ul 124 #define PDL_BSC_A12_DISABLE 0x00000020ul 125 #define PDL_BSC_A13_DISABLE 0x00000040ul 126 #define PDL_BSC_A14_DISABLE 0x00000080ul 127 #define PDL_BSC_A15_DISABLE 0x00000100ul 128 #define PDL_BSC_A16_DISABLE 0x00000200ul 129 #define PDL_BSC_A17_DISABLE 0x00000400ul 130 #define PDL_BSC_A18_DISABLE 0x00000800ul 131 #define PDL_BSC_A19_DISABLE 0x00001000ul 132 #define PDL_BSC_A20_DISABLE 0x00002000ul 133 #define PDL_BSC_A21_DISABLE 0x00004000ul 134 #define PDL_BSC_A22_DISABLE 0x00008000ul 135 #define PDL_BSC_A23_DISABLE 0x00010000ul 136 137 /* SDRAM output control */ 138 #define PDL_BSC_SDRAM_PINS_DISABLE 0x00020000ul 139 #define PDL_BSC_SDRAM_PINS_ENABLE 0x00040000ul 140 #define PDL_BSC_SDRAM_DQM1_DISABLE 0x00080000ul 141 #define PDL_BSC_SDRAM_DQM1_ENABLE 0x00100000ul 142 143 144 /* Configuration3 (error control) */ 145 /* Error monitoring */ 146 #define PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE 0x01u 147 #define PDL_BSC_ERROR_ILLEGAL_ADDRESS_DISABLE 0x02u 148 #define PDL_BSC_ERROR_TIME_OUT_ENABLE 0x04u 149 #define PDL_BSC_ERROR_TIME_OUT_DISABLE 0x08u 150 151 /* R_BSC_CreateArea parameter options */ 152 /* Configuration selection */ 153 /* Bus width */ 154 #define PDL_BSC_WIDTH_16 0x0001u 155 #define PDL_BSC_WIDTH_8 0x0002u 156 #define PDL_BSC_WIDTH_32 0x0004u 157 158 /* Endian mode */ 159 #define PDL_BSC_ENDIAN_SAME 0x0008u 160 #define PDL_BSC_ENDIAN_OPPOSITE 0x0010u 161 162 /* Write access mode */ 163 #define PDL_BSC_WRITE_BYTE 0x0020u 164 #define PDL_BSC_WRITE_SINGLE 0x0040u 165 166 /* External wait control */ 167 #define PDL_BSC_WAIT_DISABLE 0x0080u 168 #define PDL_BSC_WAIT_ENABLE 0x0100u 169 170 /* Page access control */ 171 #define PDL_BSC_PAGE_READ_DISABLE 0x0200u 172 #define PDL_BSC_PAGE_READ_NORMAL 0x0400u 173 #define PDL_BSC_PAGE_READ_CONTINUOUS 0x0800u 174 #define PDL_BSC_PAGE_WRITE_DISABLE 0x1000u 175 #define PDL_BSC_PAGE_WRITE_ENABLE 0x2000u 176 177 /* R_BSC_Control parameter options */ 178 #define PDL_BSC_ERROR_CLEAR 0x0001u 179 #define PDL_BSC_SDRAM_INITIALIZATION 0x0002u 180 #define PDL_BSC_SDRAM_AUTO_REFRESH_ENABLE 0x0004u 181 #define PDL_BSC_SDRAM_AUTO_REFRESH_DISABLE 0x0008u 182 #define PDL_BSC_SDRAM_SELF_REFRESH_ENABLE 0x0010u 183 #define PDL_BSC_SDRAM_SELF_REFRESH_DISABLE 0x0020u 184 #define PDL_BSC_SDRAM_ENABLE 0x0040u 185 #define PDL_BSC_SDRAM_DISABLE 0x0080u 186 #define PDL_BSC_DISABLE_BUSERR_IRQ 0x0100u 187 188 /* R_BSC_SDRAM_CreateArea parameter options */ 189 /* Configuration selection */ 190 /* Bus width */ 191 #define PDL_BSC_SDRAM_WIDTH_16 0x0001u 192 #define PDL_BSC_SDRAM_WIDTH_8 0x0002u 193 #define PDL_BSC_SDRAM_WIDTH_32 0x0004u 194 195 /* Endian mode */ 196 #define PDL_BSC_SDRAM_ENDIAN_SAME 0x0008u 197 #define PDL_BSC_SDRAM_ENDIAN_OPPOSITE 0x0010u 198 199 /* Continuous access mode */ 200 #define PDL_BSC_SDRAM_CONT_ACCESS_ENABLE 0x0020u 201 #define PDL_BSC_SDRAM_CONT_ACCESS_DISABLE 0x0040u 202 203 /* Address multiplex selection */ 204 #define PDL_BSC_SDRAM_8_BIT_SHIFT 0x0080u 205 #define PDL_BSC_SDRAM_9_BIT_SHIFT 0x0100u 206 #define PDL_BSC_SDRAM_10_BIT_SHIFT 0x0200u 207 #define PDL_BSC_SDRAM_11_BIT_SHIFT 0x0400u 208 209 #endif 210 /* End of file */ 211