1 /*""FILE COMMENT""*******************************************************
2 * System Name	: Serial Communication Interface API for RX62Nxx
3 * File Name		: r_pdl_sci.h
4 * Version		: 1.02
5 * Contents		: Serial Interface API header
6 * Customer		:
7 * Model			:
8 * Order			:
9 * CPU			: RX
10 * Compiler		: RXC
11 * OS			: Nothing
12 * Programmer	:
13 * Note			:
14 ************************************************************************
15 * Copyright, 2011. Renesas Electronics Corporation
16 * and Renesas Solutions Corporation
17 ************************************************************************
18 * History		: 2011.04.08
19 *				: Ver 1.02
20 *				: CS-5 release.
21 *""FILE COMMENT END""**************************************************/
22 
23 #ifndef R_PDL_SCI_H
24 #define R_PDL_SCI_H
25 
26 #include "r_pdl_common_defs_RX62Nxx.h"
27 
28 /* Function prototypes */
29 bool R_SCI_Set(
30 	uint8_t
31 );
32 bool R_SCI_Create(
33 	uint8_t,
34 	uint32_t,
35 	uint32_t,
36 	uint8_t
37 );
38 bool R_SCI_Destroy(
39 	uint8_t
40 );
41 bool R_SCI_Send(
42 	uint8_t,
43 	uint16_t,
44 	uint8_t *,
45 	uint16_t,
46 	void *
47 );
48 bool R_SCI_Receive(
49 	uint8_t,
50 	uint16_t,
51 	uint8_t *,
52 	uint16_t,
53 	void *,
54 	void *
55 );
56 bool R_SCI_Control(
57 	uint8_t,
58 	uint8_t
59 );
60 bool R_SCI_GetStatus(
61 	uint8_t,
62 	uint8_t *,
63 	uint8_t *,
64 	uint16_t *,
65 	uint16_t *
66 );
67 
68 /* ------------------------ */
69 /* R_SCI_Set, Configuration */
70 /* ------------------------ */
71 /* Pin selection */
72 #define PDL_SCI_PIN_SCI1_A	0x01u
73 #define PDL_SCI_PIN_SCI1_B	0x02u
74 #define PDL_SCI_PIN_SCI2_A	0x04u
75 #define PDL_SCI_PIN_SCI2_B	0x08u
76 #define PDL_SCI_PIN_SCI3_A	0x10u
77 #define PDL_SCI_PIN_SCI3_B	0x20u
78 #define PDL_SCI_PIN_SCI6_A	0x40u
79 #define PDL_SCI_PIN_SCI6_B	0x80u
80 
81 /* ----------------------------------------- */
82 /* R_SCI_Create, data2 Channel configuration */
83 /* ----------------------------------------- */
84 /* Operation mode */
85 #define PDL_SCI_ASYNC			0x00000001ul
86 #define PDL_SCI_SYNC			0x00000002ul
87 #define PDL_SCI_SMART			0x00000004ul
88 #define PDL_SCI_ASYNC_MP		0x00000008ul
89 
90 /* Common selections */
91 
92 /* Transmit / Receive connections */
93 #define PDL_SCI_TX_CONNECTED	0x00000010ul
94 #define PDL_SCI_TX_DISCONNECTED	0x00000020ul
95 #define PDL_SCI_RX_CONNECTED	0x00000040ul
96 #define PDL_SCI_RX_DISCONNECTED	0x00000080ul
97 
98 /* Data clock source */
99 #define PDL_SCI_CLK_INT_OUT		0x00000100ul
100 #define PDL_SCI_CLK_EXT			0x00000200ul
101 
102 /* Parity selection */
103 #define PDL_SCI_PARITY_EVEN		0x00000400ul
104 #define PDL_SCI_PARITY_ODD		0x00000800ul
105 
106 /* Asynchronous-only selections */
107 
108 /* Data clock source */
109 #define PDL_SCI_CLK_INT_IO		0x00001000ul
110 #define PDL_SCI_CLK_TMR			0x00002000ul
111 
112 /* Data length */
113 #define PDL_SCI_8_BIT_LENGTH	0x00004000ul
114 #define PDL_SCI_7_BIT_LENGTH	0x00008000ul
115 
116 /* Parity selection */
117 #define PDL_SCI_PARITY_NONE		0x00010000ul
118 
119 /* Stop bit length */
120 #define PDL_SCI_STOP_1			0x00020000ul
121 #define PDL_SCI_STOP_2			0x00040000ul
122 
123 #define PDL_SCI_8N1	(PDL_SCI_8_BIT_LENGTH | PDL_SCI_PARITY_NONE | PDL_SCI_STOP_1)
124 
125 /* Smart card-only selections */
126 
127 /* Data transfer format */
128 #define PDL_SCI_LSB_FIRST		0x00001000ul
129 #define PDL_SCI_MSB_FIRST		0x00002000ul
130 
131 /* Data inversion */
132 #define PDL_SCI_INVERSION_OFF	0x00004000ul
133 #define PDL_SCI_INVERSION_ON	0x00008000ul
134 
135 /* Base clock pulse cycle count */
136 #define PDL_SCI_BCP_32			0x00010000ul
137 #define PDL_SCI_BCP_64			0x00020000ul
138 #define PDL_SCI_BCP_93			0x00040000ul
139 #define PDL_SCI_BCP_128			0x00080000ul
140 #define PDL_SCI_BCP_186			0x00100000ul
141 #define PDL_SCI_BCP_256			0x00200000ul
142 #define PDL_SCI_BCP_372			0x00400000ul
143 #define PDL_SCI_BCP_512			0x00800000ul
144 
145 /* Block transfer mode */
146 #define PDL_SCI_BLOCK_MODE_OFF	0x01000000ul
147 #define PDL_SCI_BLOCK_MODE_ON	0x02000000ul
148 
149 /* GSM mode */
150 #define PDL_SCI_GSM_MODE_OFF	0x04000000ul
151 #define PDL_SCI_GSM_MODE_ON		0x08000000ul
152 
153 /* Clock output control */
154 #define PDL_SCI_SCK_OUTPUT_OFF	0x10000000ul
155 #define PDL_SCI_SCK_OUTPUT_LOW	0x20000000ul
156 #define PDL_SCI_SCK_OUTPUT_ON	0x40000000ul
157 #define PDL_SCI_SCK_OUTPUT_HIGH	0x80000000ul
158 
159 /* ----------------------------------- */
160 /* R_SCI_Create, data3 register value  */
161 /* ----------------------------------- */
162 /* Transfer clock control */
163 
164 /* CKS selection (optional) */
165 #define PDL_SCI_PCLK_DIV_1		0x01000000ul
166 #define PDL_SCI_PCLK_DIV_4		0x02000000ul
167 #define PDL_SCI_PCLK_DIV_16		0x03000000ul
168 #define PDL_SCI_PCLK_DIV_64		0x04000000ul
169 
170 /* ABCS selection (optional) */
171 #define PDL_SCI_CYCLE_BIT_16	0x10000000ul
172 #define PDL_SCI_CYCLE_BIT_8		0x20000000ul
173 
174 /* ----------------------------------------------- */
175 /* R_SCI_Send/R_SCI_Receive, Channel configuration */
176 /* ----------------------------------------------- */
177 /* DMAC / DTC trigger control */
178 #define PDL_SCI_DMAC_DTC_TRIGGER_DISABLE	0x0001u
179 #define PDL_SCI_DMAC_TRIGGER_ENABLE			0x0002u
180 #define PDL_SCI_DTC_TRIGGER_ENABLE			0x0004u
181 #define PDL_SCI_MP_ID_CYCLE					0x0008u
182 
183 /* ------------------------------ */
184 /* R_SCI_Control, Channel control */
185 /* ------------------------------ */
186 /* Stop control */
187 #define PDL_SCI_STOP_TX						0x01u
188 #define PDL_SCI_STOP_RX						0x02u
189 #define PDL_SCI_STOP_TX_AND_RX	(PDL_SCI_STOP_TX | PDL_SCI_STOP_RX)
190 
191 /* Break output control */
192 #define PDL_SCI_OUTPUT_MARK					0x04u
193 #define PDL_SCI_OUTPUT_SPACE				0x08u
194 
195 /* Error flag control */
196 #define PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS	0x10u
197 
198 /* Manual SCK control */
199 #define PDL_SCI_GSM_SCK_STOP				0x20u
200 #define PDL_SCI_GSM_SCK_START 				0x40u
201 
202 #endif
203 /* End of file */
204