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Searched refs:PDS_BASE (Results 1 – 25 of 25) sorted by relevance

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_pds.c644 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); in PDS_Power_On_MM_System()
652 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); in PDS_Power_On_MM_System()
657 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); in PDS_Power_On_MM_System()
662 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); in PDS_Power_On_MM_System()
667 BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); in PDS_Power_On_MM_System()
797 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
803 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntMask()
833 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
835 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
839 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
[all …]
A Dbl808_uhs_phy.c341 tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); in power_up_mm()
343 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
347 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
351 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
355 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
359 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
367 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
371 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
375 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
379 BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); in power_up_mm()
[all …]
A Dbl808_clock.c677 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); in Clock_MCU_Root_Clk_Mux_Output()
707 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7); in Clock_Get_LP_Clk_Div_Val()
1948 address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET; in CPU_Set_MTimer_RST()
2010 address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET; in CPU_Set_MTimer_CLK()
2106 address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET; in CPU_Get_MTimer_Clock()
A Dbl808_glb.c1712 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7); in GLB_Set_MCU_System_CLK_Div()
1714 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal); in GLB_Set_MCU_System_CLK_Div()
1752 *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV); in GLB_Get_MCU_System_CLK_Div()
1781 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); in GLB_Set_MCU_System_CLK()
1795 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal); in GLB_Set_MCU_System_CLK()
2427 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr); in GLB_Set_CPU_Reset_Address()
2433 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr); in GLB_Set_CPU_Reset_Address()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_pds.c339 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntEn()
347 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntEn()
396 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
404 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntMask()
490 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
494 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
498 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
556 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Clear_Reset_Event()
560 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Clear_Reset_Event()
564 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Clear_Reset_Event()
[all …]
A Dbl702_clock.c210 tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM), PDS_CLKPLL_SDMIN); in Clock_Get_AUPLL_Output()
216 … if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL), PDS_CLKPLL_POSTDIV) == 36) { in Clock_Get_AUPLL_Output()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_pds.c370 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL); in PDS_Disable_GPIO_Keep()
374 BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal); in PDS_Disable_GPIO_Keep()
378 BL_WR_REG(PDS_BASE, PDS_CTL5, tmpVal); in PDS_Disable_GPIO_Keep()
595 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
601 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntMask()
631 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
633 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
635 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
637 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
639 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
[all …]
A Dbl616_pm.c526 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in pm_pds_wakeup_src_en()
528 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in pm_pds_wakeup_src_en()
541 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in pm_pds_get_wakeup_src()
552 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in pm_pds_mask_all_wakeup_src()
554 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in pm_pds_mask_all_wakeup_src()
556 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in pm_pds_mask_all_wakeup_src()
558 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in pm_pds_mask_all_wakeup_src()
560 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in pm_pds_mask_all_wakeup_src()
562 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in pm_pds_mask_all_wakeup_src()
566 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in pm_pds_mask_all_wakeup_src()
[all …]
A Dbl616_romapi_patch.c1727 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); in PDS_Pu_PLL_Enable()
1730 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); in PDS_Pu_PLL_Enable()
1745 tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); in PDS_Pu_PLL_Disable()
1748 BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); in PDS_Pu_PLL_Disable()
1777 BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4); in PDS_Enable()
1782 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
1784 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Enable()
1786 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
1788 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Enable()
1791 BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0))); in PDS_Enable()
[all …]
A Dbl616_hbn.c1450 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL5); in HBN_Clear_PDS_Gpio_Keep()
1452 BL_WR_REG(PDS_BASE, PDS_CTL5, tmpVal); in HBN_Clear_PDS_Gpio_Keep()
1454 tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL); in HBN_Clear_PDS_Gpio_Keep()
1458 BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal); in HBN_Clear_PDS_Gpio_Keep()
A Dbl616_clock.c356 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); in Clock_MCU_Root_Clk_Mux_Output()
A Dbl616_glb.c1030 tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); in GLB_Set_MCU_System_CLK()
1047 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal); in GLB_Set_MCU_System_CLK()
1152 BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr); in GLB_Set_CPU_Reset_Address()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_pds.c147 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_Enable()
149 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Enable()
153 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_Enable()
264 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntMask()
272 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntMask()
302 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
304 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
306 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
308 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in PDS_IntClear()
310 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in PDS_IntClear()
[all …]
A Dbl602_clock.c94 tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); in Clock_Xtal_Output()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/
A Dsystem_bl602.c35 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in SystemInit()
40 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/
A Dsystem_bl702.c41 tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); in SystemInit()
46 BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/
A Dbl602_memorymap.h62 #define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/
A Dbl702_memorymap.h82 #define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/
A Dbl616_memorymap.h90 #define PDS_BASE ((uint32_t)0x2000e000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/
A Dbl808_memorymap.h95 #define PDS_BASE ((uint32_t)0x2000e000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/
A Dbl602.h173 #define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/
A Dbl702.h203 #define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/
A Dbl616.h224 #define PDS_BASE ((uint32_t)0x2000e000) macro
/bsp/bouffalo_lab/libraries/rt_drivers/
A Ddrv_sdh.c74 tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5); in sdh_clock_init()
78 BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); in sdh_clock_init()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/
A Dbl808.h439 #define PDS_BASE ((uint32_t)0x2000e000) macro

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