Searched refs:PER_BASE_40000000 (Results 1 – 3 of 3) sorted by relevance
7 #define PER_BASE_40000000 (0x40000000) macro68 #define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */69 #define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */92 #define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */93 #define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */94 #define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */95 #define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */96 #define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */97 #define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */98 #define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */[all …]
99 #define PER_BASE_40000000 (0x40000000) macro310 #define CORE_IRQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x60+ n*0x4)311 #define CORE_FIQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x70+ n*0x4)313 #define CORE_MAILBOX3_SET(n) HWREG32(PER_BASE_40000000 + 0x8C + n*0x10)314 #define CORE_MAILBOX3_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xCC + n*0x10)315 #define CORE_MAILBOX2_SET(n) HWREG32(PER_BASE_40000000 + 0x88 + n*0x10)316 #define CORE_MAILBOX2_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10)317 #define CORE_MAILBOX1_SET(n) HWREG32(PER_BASE_40000000 + 0x84 + n*0x10)318 #define CORE_MAILBOX1_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10)319 #define CORE_MAILBOX0_SET(n) HWREG32(PER_BASE_40000000 + 0x80 + n*0x10)[all …]
102 #define PER_BASE_40000000 (0x40000000) macro328 #define CORE_IRQSOURCE(n) __REG32(PER_BASE_40000000 + 0x60+ n*0x4)329 #define CORE_FIQSOURCE(n) __REG32(PER_BASE_40000000 + 0x70+ n*0x4)331 #define CORE_MAILBOX3_SET(n) __REG32(PER_BASE_40000000 + 0x8C + n*0x10)332 #define CORE_MAILBOX3_CLEAR(n) __REG32(PER_BASE_40000000 + 0xCC + n*0x10)333 #define CORE_MAILBOX2_SET(n) __REG32(PER_BASE_40000000 + 0x88 + n*0x10)334 #define CORE_MAILBOX2_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC8 + n*0x10)335 #define CORE_MAILBOX1_SET(n) __REG32(PER_BASE_40000000 + 0x84 + n*0x10)336 #define CORE_MAILBOX1_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC4 + n*0x10)337 #define CORE_MAILBOX0_SET(n) __REG32(PER_BASE_40000000 + 0x80 + n*0x10)[all …]
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