Home
last modified time | relevance | path

Searched refs:PHASE (Results 1 – 11 of 11) sorted by relevance

/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_u32k.c38 U32Kx->PHASE = U32K_PHASE_RSTValue; in U32K_DeInit()
101 U32Kx->PHASE = 65536*InitStruct->Baudrate/32768; in U32K_Init()
103 U32Kx->PHASE = 65536*InitStruct->Baudrate/8192; in U32K_Init()
236 U32Kx->PHASE = 65536*BaudRate/32768; in U32K_BaudrateConfig()
238 U32Kx->PHASE = 65536*BaudRate/8192; in U32K_BaudrateConfig()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f5xxxx_usart.h194 #define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ argument
195 (PHASE == USART_SYN_CLOCK_PHASE_SECOND))
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_usart.h200 #define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ argument
201 (PHASE == USART_SYN_CLOCK_PHASE_SECOND))
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h369 …__IO uint32_t PHASE; /*!< UART 32K x baud rate control register, Address offset:… member
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M3AH.h1684 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h2062 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h2062 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2221 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2221 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2221 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2221 …__IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) … member

Completed in 3413 milliseconds