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Searched refs:PHCFG (Results 1 – 13 of 13) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_hall_drv.h99 hall_x->PHCFG = HALL_PHCFG_DLYSEL_SET(delay_start) in hall_phase_config()
A Dhpm_qei_drv.h127 qei_x->PHCFG = QEI_PHCFG_ZCNTCFG_SET(mode) | QEI_PHCFG_PHCALIZ_SET(z_calibrate) in qei_phase_config()
A Dhpm_qeiv2_drv.h239 qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax); in qeiv2_config_phmax_phparam()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_hall_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
A Dhpm_qei_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/
A Dhpm_hall_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
A Dhpm_qei_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/
A Dhpm_hall_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
A Dhpm_qei_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_qeiv2_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/
A Dhpm_qeiv2_regs.h14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ member
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h27914 …__IOM uint32_t PHCFG; /*!< (@ 0x00000000) PHOSTIF Configureation Register … member
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h27914 …__IOM uint32_t PHCFG; /*!< (@ 0x00000000) PHOSTIF Configureation Register … member

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