Searched refs:PHY_RESET_MASK (Results 1 – 12 of 12) sorted by relevance
| /bsp/hc32/libraries/hc32_drivers/ |
| A D | drv_eth.h | 29 #define PHY_RESET_MASK (1<<15) macro
|
| A D | drv_eth.c | 503 ETH_PHY_WriteReg(ETH_PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in hc32_phy_monitor_thread()
|
| /bsp/Infineon/libraries/HAL_Drivers/ |
| A D | drv_eth.h | 22 #define PHY_RESET_MASK (1<<15) macro
|
| /bsp/hpmicro/hpm6300evk/board/ |
| A D | eth_phy_port.h | 46 #define PHY_RESET_MASK (1U << 15) macro
|
| /bsp/stm32/stm32h750-artpi/board/port/ |
| A D | drv_eth.h | 22 #define PHY_RESET_MASK (1<<15) macro
|
| A D | drv_eth.c | 178 …if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK) in rt_stm32_eth_init()
185 while(regvalue & PHY_RESET_MASK) in rt_stm32_eth_init()
|
| /bsp/at32/libraries/rt_drivers/ |
| A D | drv_emac.h | 24 #define PHY_RESET_MASK (1<<15) macro
|
| A D | drv_emac.c | 928 emac_phy_register_write(phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in phy_monitor_thread_entry()
|
| /bsp/renesas/libraries/HAL_Drivers/ |
| A D | drv_eth.h | 21 #define PHY_RESET_MASK (1<<15) macro
|
| /bsp/stm32/libraries/HAL_Drivers/drivers/ |
| A D | drv_eth.h | 21 #define PHY_RESET_MASK (1<<15) macro
|
| A D | drv_eth.c | 527 HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in phy_monitor_thread_entry()
|
| /bsp/nxp/mcx/mcxn/Libraries/drivers/ |
| A D | drv_eth.c | 42 #define PHY_RESET_MASK (1<<15) macro
316 ENET_MDIOWrite(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in phy_monitor_thread_entry()
|
Completed in 33 milliseconds