Searched refs:PIO_IFDR (Results 1 – 6 of 6) sorted by relevance
25 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ macro
1869 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P0; in hri_pio_clear_IFSR_P0_bit()1893 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P1; in hri_pio_clear_IFSR_P1_bit()1917 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P2; in hri_pio_clear_IFSR_P2_bit()1941 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P3; in hri_pio_clear_IFSR_P3_bit()1965 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P4; in hri_pio_clear_IFSR_P4_bit()1989 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P5; in hri_pio_clear_IFSR_P5_bit()2013 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P6; in hri_pio_clear_IFSR_P6_bit()2037 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P7; in hri_pio_clear_IFSR_P7_bit()2061 ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P8; in hri_pio_clear_IFSR_P8_bit()2637 ((Pio *)hw)->PIO_IFDR = ~data; in hri_pio_write_IFSR_reg()[all …]
215 base->PIO_IFDR = mask; in arch_ioport_set_port_mode()
433 AT91_REG PIO_IFDR; // Input Filter Disable Register member468 #define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Regi… macro
1506 AT91C_REG PIO_IFDR; // Input Filter Disable Register member1550 #define PIO_IFDR (AT91C_CAST(AT91C_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Re… macro
7256 __O uint32_t PIO_IFDR; /**< (PIO Offset: 0x24) Glitch Input Filter Disable Register */ member7329 …__O PIO_IFDR_Type PIO_IFDR; /**< Offset: 0x24 ( /W 32) Glitch Input Filte… member
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