Searched refs:PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
239 PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK | in pixelmux_config_lvds_tx_phy0_clk()
658 #define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU) macro660 …int32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK)661 …ELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) …
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