Searched refs:PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (Results 1 – 1 of 1) sorted by relevance
901 #define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL) macro903 …int32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK)904 …ELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) …
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