Searched refs:PL (Results 1 – 10 of 10) sorted by relevance
15 ptr->PL[gpio_index].TOGGLE = 1 << pin_index; in gpio_toggle_pin_interrupt_trigger_polarity()39 ptr->PL[gpio_index].CLEAR = 1 << pin_index; in gpio_config_pin_interrupt()41 ptr->PL[gpio_index].SET = 1 << pin_index; in gpio_config_pin_interrupt()51 ptr->PL[gpio_index].CLEAR = 1 << pin_index; in gpio_config_pin_interrupt()53 ptr->PL[gpio_index].SET = 1 << pin_index; in gpio_config_pin_interrupt()
157 PinH17:PL.6175 PinJ17:PL.7193 PinK17:PL.8211 PinL17:PL.9212 PinL18:PL.3230 PinM18:PL.0248 PinN18:PL.1266 PinP18:PL.2
17 …e Logic(PL)技术将四核ARM Cortex-A53 和FPGA 可编程逻辑集成在一颗芯片上。另外核心板上 PS 端带有 4 片共 4GB 高速 DDR4 SDRAM 芯片,1 片 8GB…
5 正点原子 DFZU2EG MPSoC 开发板采用Xilinx的Zynq UltraScale+ MPSoC芯片作为主控芯片。它主要分为PS和PL两部分,在PS部分中主要由Arm Cortex A53…
44 } PL[16]; member
49 } PL[15]; member
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