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Searched refs:PLL0CON (Results 1 – 2 of 2) sorted by relevance

/bsp/bluetrum/libraries/hal_libraries/bmsis/source/
A Dsystem_ab32vgx.c278 PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5)); in set_sysclk_do()
279 …PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则… in set_sysclk_do()
280 PLL0CON |= BIT(20); //update pll0div to pll0_clk in set_sysclk_do()
399 if (!(PLL0CON & BIT(12))) { in set_sysclk()
400 PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5)); in set_sysclk()
401 …PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则为… in set_sysclk()
402 PLL0CON |= BIT(12); //enable pll0 ldo in set_sysclk()
405 PLL0CON |= BIT(20); //update pll0div to pll0_clk in set_sysclk()
406 PLL0CON |= BIT(6); //enable analog pll0 in set_sysclk()
407 PLL0CON |= BIT(18); //pll0 sdm enable in set_sysclk()
/bsp/bluetrum/libraries/hal_libraries/bmsis/include/
A Dab32vg1.h171 #define PLL0CON SFR_RW (SFR3_BASE + 0x26*4) macro

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