Searched refs:PLL0DIV (Results 1 – 2 of 2) sorted by relevance

/bsp/bluetrum/libraries/hal_libraries/bmsis/source/
A D	system_ab32vgx.c	276 if (PLL0DIV != (240 * 65536 / 26)) { in set_sysclk_do() 277 PLL0DIV = 240 * 65536 / 26; //pll: 240M, XOSC: 26M in set_sysclk_do() 404 PLL0DIV = 240 * 65536 / 26; //pll0: 240M, XOSC: 26M in set_sysclk()
/bsp/bluetrum/libraries/hal_libraries/bmsis/include/
A D	ab32vg1.h	169 #define PLL0DIV SFR_RW (SFR3_BASE + 0x23*4) macro

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