Home
last modified time | relevance | path

Searched refs:PLL1CON (Results 1 – 2 of 2) sorted by relevance

/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/
A Ddrv_sound.c39 PLL1CON &= ~(BIT(16) | BIT(17)); //PLL1 refclk select xosc26m in adpll_init()
42 PLL1CON &= ~(BIT(3) | BIT(4) | BIT(5)); in adpll_init()
43 …PLL1CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = … in adpll_init()
45 PLL1CON |= BIT(12); //enable pll1 ldo in adpll_init()
47 PLL1CON |= BIT(18); //pll1 sdm enable in adpll_init()
59 PLL1CON |= BIT(20); //update pll1div in adpll_init()
60 PLL1CON |= BIT(6); //enable analog pll1 in adpll_init()
/bsp/bluetrum/libraries/hal_libraries/bmsis/include/
A Dab32vg1.h172 #define PLL1CON SFR_RW (SFR3_BASE + 0x27*4) macro

Completed in 8 milliseconds