Searched refs:PLL1DIV (Results 1 – 2 of 2) sorted by relevance

/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/
A D	drv_sound.c	51 PLL1DIV = (245.76 * 65536) / 26; //245.76Mhz for 48K in adpll_init() 55 PLL1DIV = (248.3712 * 65536) / 26; //248.3712MHz for 44.1k in adpll_init()
/bsp/bluetrum/libraries/hal_libraries/bmsis/include/
A D	ab32vg1.h	170 #define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4) macro

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