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Searched refs:PLLCFGR (Results 1 – 25 of 50) sorted by relevance

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/bsp/mm32/mm32f3270-100ask-pitaya/board/
A Dboard.c39 RCC->PLLCFGR |= (1<<0); // 配置PLL的时钟源HSE in SystemClock_Config()
40 RCC->PLLCFGR &= ~(1<<1); // 配置PLL的时钟源HSE不分频后再作为时钟输入源 in SystemClock_Config()
41 RCC->PLLCFGR &= ~(0x7F<<16); in SystemClock_Config()
42 RCC->PLLCFGR |= (19<<16); // 配置PLL的倍频系数:20倍 -> 12MHz/2*20 = 120MHz in SystemClock_Config()
43 RCC->PLLCFGR &= ~(0x7<<8); in SystemClock_Config()
44 RCC->PLLCFGR |= (1<<8); // 配置PLL的分频系数:2 in SystemClock_Config()
91 if(RCC->PLLCFGR&0x01) // HSE用作PLL的输入时钟 in update_systemclock()
93 if(RCC->PLLCFGR&0x02) // HSE二分频后输入给PLL in update_systemclock()
106 prediv = (RCC->PLLCFGR>>8)&0x07; // PLL的分频系数：PLLCFGR[10:8] in update_systemclock()
107 pllmul = (RCC->PLLCFGR>>16)&0x7F; // PLL的倍频系数: PLLCFGR[22:16] in update_systemclock()
/bsp/mm32f327x/Libraries/MM32F327x/Source/
A Dsystem_mm32f327x.c383 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo24()
456 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo36()
529 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo48()
628 RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; in SetSysClockToXX()
629 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockToXX()
635 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockToXX()
675 RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; in SetSysClockTo24_HSI()
676 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo24_HSI()
709 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo36_HSI()
746 RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; in SetSysClockTo48_HSI()
[all …]
/bsp/stm32/stm32g474-st-nucleo/board/CubeMX_Config/Src/
A Dsystem_stm32g4xx.c232 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); in SystemCoreClockUpdate()
233 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; in SystemCoreClockUpdate()
242 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); in SystemCoreClockUpdate()
243 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; in SystemCoreClockUpdate()
/bsp/stm32/stm32g491-st-nucleo/board/CubeMX_Config/Core/Src/
A Dsystem_stm32g4xx.c247 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); in SystemCoreClockUpdate()
248 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; in SystemCoreClockUpdate()
257 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); in SystemCoreClockUpdate()
258 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; in SystemCoreClockUpdate()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/
A Dsystem_ht32f5xxxx_10.c349 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
352 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
354 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
407 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
408 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
409 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_03.c397 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
400 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
402 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
464 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
465 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
466 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_05.c389 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
392 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
394 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
447 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
448 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
449 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_06.c376 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
379 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
381 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
434 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
435 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
436 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_08.c397 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
400 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
402 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
462 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
463 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
464 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_09.c377 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
380 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
382 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
435 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
436 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
437 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_11.c398 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
401 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
403 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
456 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
457 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
458 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_12.c373 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
376 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
378 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
431 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
432 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
433 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_14.c377 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
380 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
382 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
435 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
436 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
437 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_15.c375 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
378 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
380 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
433 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
434 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
435 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_16.c353 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
356 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
358 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
422 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
423 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
424 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_17.c376 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
379 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
381 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
434 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
435 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
436 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_18.c388 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
391 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
393 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
455 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
456 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
457 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f0006.c375 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
425 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
426 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_07.c379 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
429 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
430 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5826.c401 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
453 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
454 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_01.c413 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
465 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
466 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_02.c426 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
478 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
479 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
/bsp/stm32/stm32l496-st-discovery/board/CubeMX_Config/Src/
A Dsystem_stm32l4xx.c286 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); in SystemCoreClockUpdate()
287 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; in SystemCoreClockUpdate()
303 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); in SystemCoreClockUpdate()
304 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; in SystemCoreClockUpdate()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/
A Dsystem_ht32f1xxxx_03.c391 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
394 …SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider … in SystemInit()
396 …ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider … in SystemInit()
472 u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; in SystemCoreClockUpdate()
473 …u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> … in SystemCoreClockUpdate()
474 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()
A Dsystem_ht32f1xxxx_01.c360 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x3F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
417 u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (64) : (HT_CKCU->PLLCFGR >> 23); in SystemCoreClockUpdate()
418 u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; in SystemCoreClockUpdate()

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