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Searched refs:PLLCR (Results 1 – 25 of 72) sorted by relevance

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/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DSystem_ACM32F4.c183 SCU->PLLCR |= SCU_PLLCR_PLL_EN; in System_Clock_Init()
184 SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); in System_Clock_Init()
185 while(!(SCU->PLLCR & SCU_PLLCR_PLL_FREE_RUN)); in System_Clock_Init()
191 SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (33 << 3); in System_Clock_Init()
201 SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (18U << 3); in System_Clock_Init()
232 SCU->PLLCR |= SCU_PLLCR_PLL_EN; in System_Clock_Init()
233 SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); in System_Clock_Init()
240 … SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (1U << 12) | (0U << 16); in System_Clock_Init()
241 SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); in System_Clock_Init()
251 … SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (2U << 12) | (0U << 16); in System_Clock_Init()
[all …]
/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DSystem_ACM32F0x0.c158 SCU->PLLCR |= SCU_PLLCR_PLL_EN; in System_Clock_Init()
159 SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); in System_Clock_Init()
160 while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) )) {} in System_Clock_Init()
163 SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (1U << 12) | (0U << 16); in System_Clock_Init()
167 SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (2U << 12) | (0U << 16); in System_Clock_Init()
170 SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); in System_Clock_Init()
171 SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; in System_Clock_Init()
172 while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); in System_Clock_Init()
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/
A Dsystem_fm33lc0xx.c56 switch ((RCC->PLLCR >> 1) & 0x1) in SystemPLLClockUpdate()
82 switch ((RCC->PLLCR >> 0x4) & 0x7) in SystemPLLClockUpdate()
118 clock = clock * (((RCC->PLLCR >> 16) & 0x7F) + 1); in SystemPLLClockUpdate()
121 if ((RCC->PLLCR >> 3) & 0x1) in SystemPLLClockUpdate()
228 RCC->PLLCR = 0x00000000U; in SystemInit()
/bsp/synwit/libraries/SWM320_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM320.c103 if(SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC in SystemCoreClockUpdate()
248 SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); in switchCLK_PLL()
263 SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC in PLLInit()
272 SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL in PLLInit()
282 SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos); in PLLInit()
/bsp/synwit/libraries/SWM341_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM341.c101 if(SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_IN <= HRC in SystemCoreClockUpdate()
384 SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC in PLLInit()
395 SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL in PLLInit()
405 SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos); in PLLInit()
409 SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); in PLLInit()
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_rcc.h1008 SET_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk); in FL_RCC_PLL_Enable()
1018 CLEAR_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk); in FL_RCC_PLL_Disable()
1028 return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_EN_Msk) == RCC_PLLCR_EN_Msk); in FL_RCC_PLL_IsEnabled()
1051 MODIFY_REG(RCC->PLLCR, RCC_PLLCR_INSEL_Msk, clock); in FL_RCC_PLL_SetClockSource()
1063 return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_INSEL_Msk)); in FL_RCC_PLL_GetClockSource()
1074 MODIFY_REG(RCC->PLLCR, (0x7fU << 16U), (multiplier << 16U)); in FL_RCC_PLL_WriteMultiplier()
1084 return (uint32_t)(READ_BIT(RCC->PLLCR, (0x7fU << 16U)) >> 16U); in FL_RCC_PLL_ReadMultiplier()
1103 MODIFY_REG(RCC->PLLCR, RCC_PLLCR_REFPRSC_Msk, prescaler); in FL_RCC_PLL_SetPrescaler()
1121 return (uint32_t)(READ_BIT(RCC->PLLCR, RCC_PLLCR_REFPRSC_Msk)); in FL_RCC_PLL_GetPrescaler()
1134 MODIFY_REG(RCC->PLLCR, RCC_PLLCR_OSEL_Msk, multiplier); in FL_RCC_PLL_SetOutputMultiplier()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_ckcu.c196 …HT_CKCU->PLLCR = 0; /* Reset value of PLLCR … in CKCU_DeInit()
344 CKCU_BF_WRITE(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS, PLL_InitStruct->BYPASSCmd); in CKCU_PLLInit()
607 u32 CKCU_BB_PLLBYPASS = CKCU_BF_READ(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS); in CKCU_GetPLLFrequency()
/bsp/fm33lc026/board/
A Dboard.c104 …MODIFY_REG(RCC->PLLCR, RCC_PLLCR_DB_Msk | RCC_PLLCR_REFPRSC_Msk | RCC_PLLCR_OSEL_Msk | RCC_PLLCR_I… in RCC_PLL_ConfigDomain_SYS()
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c173 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c173 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c173 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/renesas/ra8m1-ek/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c173 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c159 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/mcu/all/
A Dbsp_common.c159 (uint32_t) &R_SYSTEM->PLLCR, in R_BSP_NSC_STYPE3_RegU8Read()
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/
A Dsystem_ht32f0006.c432 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_07.c436 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_10.c415 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5826.c460 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_01.c472 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_02.c485 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_03.c472 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_05.c455 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
A Dsystem_ht32f5xxxx_06.c442 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/
A Dsystem_ht32f1xxxx_01.c424 if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) in SystemCoreClockUpdate()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_ckcu.c130 #define CKCU_BB_PLLBYPASS BitBand((u32)&HT_CKCU->PLLCR, 31)
186 …HT_CKCU->PLLCR = 0; /* Reset value of PLLCR … in CKCU_DeInit()

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