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Searched refs:PLLCTL_PLL_CFG0_POSTDIV1_SET (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_pllctl_drv.h203 …G0 = ((ptr->PLL[pll].CFG0 & ~(PLLCTL_PLL_CFG0_POSTDIV1_MASK))) | PLLCTL_PLL_CFG0_POSTDIV1_SET(div); in pllctl_set_postdiv1()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_pllctl_regs.h96 #define PLLCTL_PLL_CFG0_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL… macro

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