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Searched refs:PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_pllctl_regs.h144 #define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK (0x20U) macro
146 …) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK)
147 … PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >>…
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_pllctl_drv.h92 ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; in pllctl_pll_ss_disable()
175 ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; in pllctl_pll_ss_enable()

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