PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (reference) in projects: bsp

Searched refs:PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A D	hpm_pllctl_regs.h	`114 #define PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (0x3F00U) macro 116 …DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) 117 #define PLLCTL_PLL_CFG0_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCT…`
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A D	hpm_pllctl_drv.h	`166 \|\| (div > (PLLCTL_PLL_CFG0_SS_DIVVAL_MASK >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT))) { in pllctl_pll_ss_enable() 177 & ~(PLLCTL_PLL_CFG0_SS_SPREAD_MASK \| PLLCTL_PLL_CFG0_SS_DIVVAL_MASK)) in pllctl_pll_ss_enable()`

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