PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (reference) in projects: bsp

Searched refs:PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A D	hpm_pllctl_regs.h	`115 #define PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (8U) macro 116 #define PLLCTL_PLL_CFG0_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLC… 117 …DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT)`
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A D	hpm_pllctl_drv.h	`166 \|\| (div > (PLLCTL_PLL_CFG0_SS_DIVVAL_MASK >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT))) { in pllctl_pll_ss_enable()`

Completed in 6 milliseconds