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Searched refs:PLLCTL_PLL_CFG0_SS_RESET_MASK (Results 1 – 2 of 2) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_pllctl_regs.h135 #define PLLCTL_PLL_CFG0_SS_RESET_MASK (0x40U) macro
137 …SS_RESET_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK)
138 #define PLLCTL_PLL_CFG0_SS_RESET_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_…
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_pllctl_drv.h91 | PLLCTL_PLL_CFG0_SS_RESET_MASK); in pllctl_pll_ss_disable()
174 | PLLCTL_PLL_CFG0_SS_RESET_MASK); in pllctl_pll_ss_enable()

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