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Searched refs:PLLDIV (Results 1 – 11 of 11) sorted by relevance

/bsp/synwit/libraries/SWM320_CSL/SWM320_StdPeriph_Driver/
A DSWM320_adc.c59 SYS->PLLDIV &= ~SYS_PLLDIV_ADVCO_Msk; in ADC_Init()
60 SYS->PLLDIV |= ((initStruct->clk_src - 2) << SYS_PLLDIV_ADVCO_Pos); in ADC_Init()
62 SYS->PLLDIV &= ~SYS_PLLDIV_ADDIV_Msk; in ADC_Init()
63 SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); in ADC_Init()
/bsp/synwit/libraries/SWM320_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM320.c275 SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk | in PLLInit()
278 SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) | in PLLInit()
A DSWM320.h175 __IO uint32_t PLLDIV; member
/bsp/synwit/libraries/SWM341_CSL/CMSIS/DeviceSupport/
A Dsystem_SWM341.c398 SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk | in PLLInit()
401 SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) | in PLLInit()
A DSWM341.h237 __IO uint32_t PLLDIV; member
/bsp/stm32/stm32l010-st-nucleo/board/
A Dboard.c33 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; in SystemClock_Config()
/bsp/stm32/stm32l053-st-nucleo/board/
A Dboard.c33 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; in SystemClock_Config()
/bsp/stm32/libraries/templates/stm32l1xx/board/
A Dboard.c31 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; in SystemClock_Config()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal_rcc.c695 assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); in HAL_RCC_OscConfig()
715 RCC_OscInitStruct->PLL.PLLDIV); in HAL_RCC_OscConfig()
762 (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) in HAL_RCC_OscConfig()
1260 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); in HAL_RCC_GetOscConfig()
/bsp/stm32/libraries/templates/stm32l1xx/board/CubeMX_Config/
A Dstm32l151cb.ioc116 …SE_VALUE,HSI_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLDIV,PLLMUL,PWRFreq_Val…
121 RCC.PLLDIV=RCC_PLL_DIV3
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_rcc.h245 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock member

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