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Searched refs:PLLSRC_DIV (Results 1 – 7 of 7) sorted by relevance

/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/
A Dsystem_n32l43x.c131 #define PLLSRC_DIV 2 macro
137 #define PLLSRC_DIV 1 macro
144 #define PLLSRC_DIV 2 macro
161 #define PLLSRC_DIV 2 macro
167 #define PLLSRC_DIV 1 macro
174 #define PLLSRC_DIV 2 macro
580 …rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2… in SetSysClock()
582 rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/
A Dsystem_n32l40x.c132 #define PLLSRC_DIV 2 macro
138 #define PLLSRC_DIV 1 macro
145 #define PLLSRC_DIV 2 macro
162 #define PLLSRC_DIV 2 macro
168 #define PLLSRC_DIV 1 macro
175 #define PLLSRC_DIV 2 macro
584 …rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2… in SetSysClock()
586 rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/
A Dsystem_n32g43x.c131 #define PLLSRC_DIV 2 macro
137 #define PLLSRC_DIV 1 macro
144 #define PLLSRC_DIV 2 macro
161 #define PLLSRC_DIV 2 macro
167 #define PLLSRC_DIV 1 macro
174 #define PLLSRC_DIV 2 macro
580 …rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2… in SetSysClock()
582 rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/
A Dsystem_n32g4fr.c95 #define PLLSRC_DIV 2 macro
111 #define PLLSRC_DIV 2 macro
116 #define PLLSRC_DIV 1 macro
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/
A Dsystem_n32g45x.c95 #define PLLSRC_DIV 2 macro
111 #define PLLSRC_DIV 2 macro
116 #define PLLSRC_DIV 1 macro
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/
A Dsystem_n32wb452.c95 #define PLLSRC_DIV 2 macro
111 #define PLLSRC_DIV 2 macro
116 #define PLLSRC_DIV 1 macro
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/
A Dsystem_n32g45x.c95 #define PLLSRC_DIV 2 macro
111 #define PLLSRC_DIV 2 macro
116 #define PLLSRC_DIV 1 macro
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()

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