Searched refs:PLL_NF2_DIV (Results 1 – 21 of 21) sorted by relevance

/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/
A D	system_ht32f0006.c	133 #define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 … macro 210 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 216 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 375 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_07.c	137 #define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 … macro 214 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 220 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 379 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_10.c	134 #define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 … macro 203 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 209 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 349 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5826.c	137 #define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 … macro 216 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 222 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 401 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_01.c	149 #define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 … macro 228 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 234 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 413 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_02.c	162 #define PLL_NF2_DIV (5) /*!< 1~16: DIV1~DIV16 … macro 241 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 247 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 426 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_03.c	153 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 230 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 236 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 397 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_05.c	151 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 227 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 233 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 389 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_06.c	138 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 214 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 220 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 376 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_08.c	146 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 230 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 236 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 397 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_09.c	139 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 215 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 221 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 377 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_12.c	137 #define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 … macro 213 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 219 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 373 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_14.c	141 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 217 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 223 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 377 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_15.c	139 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 215 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 221 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 375 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_16.c	137 #define PLL_NF2_DIV (20) /*!< 1~32: DIV1~DIV32 … macro 207 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 213 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 353 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_17.c	140 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 216 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 222 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 376 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_18.c	144 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 221 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source… 227 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source … 388 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f5xxxx_11.c	145 #define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 … macro 249 …#define __CK_VCO (__CK_PLL_SRC * PLL_NF2_DIV) /*!< Get CK_VCO frequency … 398 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/
A D	system_ht32f1xxxx_01.c	134 #define PLL_NF2_DIV (18) /*!< 1~64: DIV1~DIV64 … macro 212 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 218 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 360 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x3F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f1xxxx_02.c	141 #define PLL_NF2_DIV (12) /*!< 1~32: DIV1~DIV32 … macro 219 …#define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source … 225 …#define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source … 403 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()
A D	system_ht32f1xxxx_03.c	144 #define PLL_NF2_DIV (9) /*!< 1~32: DIV1~DIV32 … macro 222 …#define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as … 228 …#define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as … 391 …HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider … in SystemInit()

Completed in 55 milliseconds

Last Index update Fri Aug 22 02:45:11 CST 2025