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Searched refs:PMU (Results 1 – 25 of 126) sorted by relevance

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/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/
A Dapm32f4xx_pmu.c64 PMU->CTRL_B.BPWEN = ENABLE; in PMU_EnableBackupAccess()
76 PMU->CTRL_B.BPWEN = DISABLE; in PMU_DisableBackupAccess()
88 PMU->CTRL_B.PVDEN = ENABLE; in PMU_EnablePVD()
100 PMU->CTRL_B.PVDEN = DISABLE; in PMU_DisablePVD()
121 PMU->CTRL_B.PLSEL = 0; in PMU_ConfigPVDLevel()
122 PMU->CTRL_B.PLSEL = level; in PMU_ConfigPVDLevel()
158 PMU->CSTS_B.BKPREN = ENABLE; in PMU_EnableBackupRegulator()
184 PMU->CTRL_B.VOSSEL = 0; in PMU_ConfigMainRegulatorMode()
185 PMU->CTRL_B.VOSSEL = scale; in PMU_ConfigMainRegulatorMode()
230 PMU->CTRL_B.PDDSCFG = 0x00; in PMU_EnterSTOPMode()
[all …]
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_pmu.c58 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_lvd_irq_handler()
99 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); in ald_pmu_stop1_enter()
101 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); in ald_pmu_stop1_enter()
127 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); in ald_pmu_stop2_enter()
129 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); in ald_pmu_stop2_enter()
178 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); in ald_pmu_ldo_12_config()
223 SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK); in ald_pmu_lprun_config()
243 if (READ_BIT(PMU->SR, sr)) in ald_pmu_get_status()
260 SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK); in ald_pmu_clear_status()
284 SET_BIT(PMU->PWRCR, perh); in ald_pmu_perh_power_config()
[all …]
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_pmu.c64 PMU->CTRL_B.BPWEN = ENABLE ; in PMU_EnableBackupAccess()
76 PMU->CTRL_B.BPWEN = DISABLE; in PMU_DisableBackupAccess()
88 PMU->CTRL_B.PVDEN = ENABLE; in PMU_EnablePVD()
100 PMU->CTRL_B.PVDEN = DISABLE; in PMU_DisablePVD()
123 PMU->CTRL_B.PLSEL = 0x0000; in PMU_ConfigPVDLevel()
125 PMU->CTRL_B.PLSEL = level; in PMU_ConfigPVDLevel()
137 PMU->CSTS_B.WKUPCFG = ENABLE ; in PMU_EnableWakeUpPin()
149 PMU->CSTS_B.WKUPCFG = DISABLE ; in PMU_DisableWakeUpPin()
170 PMU->CTRL_B.PDDSCFG = 0x00; in PMU_EnterSTOPMode()
171 PMU->CTRL_B.LPDSCFG = 0x00; in PMU_EnterSTOPMode()
[all …]
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_pmu.c64 PMU->CTRL_B.BPWEN = ENABLE ; in PMU_EnableBackupAccess()
76 PMU->CTRL_B.BPWEN = DISABLE; in PMU_DisableBackupAccess()
88 PMU->CTRL_B.PVDEN = ENABLE; in PMU_EnablePVD()
100 PMU->CTRL_B.PVDEN = DISABLE; in PMU_DisablePVD()
123 PMU->CTRL_B.PLSEL = 0x0000; in PMU_ConfigPVDLevel()
125 PMU->CTRL_B.PLSEL = level; in PMU_ConfigPVDLevel()
137 PMU->CSTS_B.WKUPCFG = ENABLE ; in PMU_EnableWakeUpPin()
149 PMU->CSTS_B.WKUPCFG = DISABLE ; in PMU_DisableWakeUpPin()
170 PMU->CTRL_B.PDDSCFG = 0x00; in PMU_EnterSTOPMode()
171 PMU->CTRL_B.LPDSCFG = 0x00; in PMU_EnterSTOPMode()
[all …]
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/src/
A Dapm32s10x_pmu.c64 PMU->CTRL_B.BPWEN = ENABLE ; in PMU_EnableBackupAccess()
76 PMU->CTRL_B.BPWEN = DISABLE; in PMU_DisableBackupAccess()
88 PMU->CTRL_B.PVDEN = ENABLE; in PMU_EnablePVD()
100 PMU->CTRL_B.PVDEN = DISABLE; in PMU_DisablePVD()
122 PMU->CTRL_B.PLSEL = 0x0000; in PMU_ConfigPVDLevel()
124 PMU->CTRL_B.PLSEL = level; in PMU_ConfigPVDLevel()
136 PMU->CSTS_B.WKUPCFG = ENABLE ; in PMU_EnableWakeUpPin()
148 PMU->CSTS_B.WKUPCFG = DISABLE ; in PMU_DisableWakeUpPin()
169 PMU->CTRL_B.PDDSCFG = 0x00; in PMU_EnterSTOPMode()
170 PMU->CTRL_B.LPDSCFG = 0x00; in PMU_EnterSTOPMode()
[all …]
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_pmu.c54 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_lvd_irq_handler()
91 if (READ_BIT(PMU->SR, sr)) in ald_pmu_get_status()
108 SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); in ald_pmu_clear_status()
128 CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); in ald_pmu_stop_enter()
191 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); in ald_pmu_lvd_config()
192 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_pmu_lvd_config()
193 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); in ald_pmu_lvd_config()
194 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); in ald_pmu_lvd_config()
197 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_pmu_lvd_config()
198 CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); in ald_pmu_lvd_config()
[all …]
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_wdt.c25 PMU->WDTPASS = WDTPASS_KEY; in WDT_Enable()
26 PMU->WDTEN |= PMU_WDTEN_WDTEN; in WDT_Enable()
28 PMU->WDTPASS = WDTPASS_KEY; in WDT_Enable()
29 PMU->WDTEN |= PMU_WDTEN_WDTEN; in WDT_Enable()
39 PMU->WDTPASS = WDTPASS_KEY; in WDT_Disable()
40 PMU->WDTEN &= ~PMU_WDTEN_WDTEN; in WDT_Disable()
42 PMU->WDTPASS = WDTPASS_KEY; in WDT_Disable()
53 PMU->WDTCLR = WDTCLR_KEY; in WDT_Clear()
71 tmp = PMU->WDTEN; in WDT_SetPeriod()
74 PMU->WDTPASS = WDTPASS_KEY; in WDT_SetPeriod()
[all …]
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_wdt.c25 PMU->WDTPASS = WDTPASS_KEY; in WDT_Enable()
26 PMU->WDTEN |= PMU_WDTEN_WDTEN; in WDT_Enable()
28 PMU->WDTPASS = WDTPASS_KEY; in WDT_Enable()
29 PMU->WDTEN |= PMU_WDTEN_WDTEN; in WDT_Enable()
39 PMU->WDTPASS = WDTPASS_KEY; in WDT_Disable()
40 PMU->WDTEN &= ~PMU_WDTEN_WDTEN; in WDT_Disable()
42 PMU->WDTPASS = WDTPASS_KEY; in WDT_Disable()
53 PMU->WDTCLR = WDTCLR_KEY; in WDT_Clear()
71 tmp = PMU->WDTEN; in WDT_SetPeriod()
74 PMU->WDTPASS = WDTPASS_KEY; in WDT_SetPeriod()
[all …]
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_pmu.c56 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_lvd_irq_handler()
112 SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); in ald_pmu_stop2_enter()
135 SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); in ald_pmu_standby_enter()
156 if (READ_BIT(PMU->SR, sr)) in ald_pmu_get_status()
173 SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); in ald_pmu_clear_status()
175 SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); in ald_pmu_clear_status()
217 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); in ald_pmu_lvd_config()
218 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); in ald_pmu_lvd_config()
219 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); in ald_pmu_lvd_config()
220 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); in ald_pmu_lvd_config()
[all …]
/bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/
A Dapm32f0xx_pmu.c87 PMU->CTRL_B.BPWEN = BIT_SET; in PMU_EnableBackupAccess()
99 PMU->CTRL_B.BPWEN = BIT_RESET; in PMU_DisableBackupAccess()
122 PMU->CTRL_B.PLSEL = level; in PMU_ConfigPVDLevel()
136 PMU->CTRL_B.PVDEN = BIT_SET; in PMU_EnablePVD()
149 PMU->CTRL_B.PVDEN = BIT_RESET; in PMU_DisablePVD()
170 PMU->CSTS |= pin; in PMU_EnableWakeUpPin()
191 PMU->CSTS &= ~pin; in PMU_DisableWakeUpPin()
238 PMU->CTRL_B.PDDSCFG = BIT_RESET; in PMU_EnterSTOPMode()
240 PMU->CTRL_B.LPDSCFG = regulator; in PMU_EnterSTOPMode()
275 PMU->CTRL_B.PDDSCFG = BIT_SET; in PMU_EnterSTANDBYMode()
[all …]
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_RTC.c40 PMU->CR1 |= RPMU_CR_RTCEN; in HAL_RTC_Config()
46 PMU->ANACR |= RPMU_ANACR_RC32K_EN; in HAL_RTC_Config()
49 PMU->CR1 &= ~RTC_CLOCK_XTL; in HAL_RTC_Config()
54 … PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); in HAL_RTC_Config()
56 PMU->ANACR |= RPMU_ANACR_XTLEN; in HAL_RTC_Config()
59 PMU->CR1 |= RTC_CLOCK_XTL; in HAL_RTC_Config()
402 PMU->CR1 |= fe_Wakeup << 8; in HAL_RTC_Standby_Wakeup()
404 PMU->CR1 |= fe_Wakeup; in HAL_RTC_Standby_Wakeup()
414 PMU->CR2 |= fe_Wakeup >> 16; in HAL_RTC_Standby_Wakeup()
456 if (PMU->SR & RPMU_SR_SBF) in HAL_RTC_Get_StandbyStatus()
[all …]
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_RTC.c40 PMU->CR1 |= RPMU_CR_RTCEN; in HAL_RTC_Config()
46 PMU->ANACR |= RPMU_ANACR_RC32K_EN; in HAL_RTC_Config()
49 PMU->CR1 &= ~RTC_CLOCK_XTL; in HAL_RTC_Config()
54 … PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); in HAL_RTC_Config()
56 PMU->ANACR |= RPMU_ANACR_XTLEN; in HAL_RTC_Config()
59 PMU->CR1 |= RTC_CLOCK_XTL; in HAL_RTC_Config()
402 PMU->CR1 |= fe_Wakeup << 8; in HAL_RTC_Standby_Wakeup()
404 PMU->CR1 |= fe_Wakeup; in HAL_RTC_Standby_Wakeup()
414 PMU->CR2 |= fe_Wakeup >> 16; in HAL_RTC_Standby_Wakeup()
456 if (PMU->SR & RPMU_SR_SBF) in HAL_RTC_Get_StandbyStatus()
[all …]
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/
A DHAL_RTC.h465 #define __HAL_RTC_PC13_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3)) | (__FUNC__))
470 #define __HAL_RTC_PC14_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 3)) | (__FUNC__ << 3))
476 #define __HAL_RTC_PC15_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 5)) | (__FUNC__ << 5))
482 #define __HAL_RTC_PC13_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 8)) | (__VALUE__ << …
488 #define __HAL_RTC_PC14_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 9)) | (__VALUE__ << …
494 #define __HAL_RTC_PC15_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 10)) | (__VALUE__ <<…
513 #define __HAL_RTC_PC13_ANALOG() (PMU->IOCR |= BIT6)
514 #define __HAL_RTC_PC13_DIGIT() (PMU->IOCR &= ~BIT6)
516 #define __HAL_RTC_PC14_ANALOG() (PMU->IOCR |= BIT14)
517 #define __HAL_RTC_PC14_DIGIT() (PMU->IOCR &= ~BIT14)
[all …]
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Inc/
A DHAL_RTC.h466 #define __HAL_RTC_PC13_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3)) | (__FUNC__))
472 #define __HAL_RTC_PC14_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 3)) | (__FUNC__ << 3))
478 #define __HAL_RTC_PC15_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 5)) | (__FUNC__ << 5))
484 #define __HAL_RTC_PC13_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 8)) | (__VALUE__ << …
490 #define __HAL_RTC_PC14_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 9)) | (__VALUE__ << …
496 #define __HAL_RTC_PC15_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 10)) | (__VALUE__ <<…
515 #define __HAL_RTC_PC13_ANALOG() (PMU->IOCR |= BIT6)
516 #define __HAL_RTC_PC13_DIGIT() (PMU->IOCR &= ~BIT6)
518 #define __HAL_RTC_PC14_ANALOG() (PMU->IOCR |= BIT14)
519 #define __HAL_RTC_PC14_DIGIT() (PMU->IOCR &= ~BIT14)
[all …]
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Include/
A Dald_pmu.h57 SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
63 CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
69 CLEAR_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \
75 SET_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \
81 SET_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \
87 CLEAR_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \
93 SET_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \
99 CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \
105 SET_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \
111 CLEAR_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
277 return PMU->EVCNTR[num]; in ARM_PMU_Get_EVCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
277 return PMU->EVCNTR[num]; in ARM_PMU_Get_EVCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
[all …]
/bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dpmu_armv8.h200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
218 PMU->EVTYPER[num] = type; in ARM_PMU_Set_EVTYPER()
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
267 return PMU->CCNTR; in ARM_PMU_Get_CCNTR()
288 return PMU->OVSSET; in ARM_PMU_Get_CNTR_OVS()
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
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Completed in 728 milliseconds

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