1 /**
2 *********************************************************************************
3 *
4 * @file ald_pmu.h
5 * @brief Header file of PMU module driver.
6 *
7 * @version V1.0
8 * @date 04 Dec 2019
9 * @author AE Team
10 * @note
11 * Change Logs:
12 * Date Author Notes
13 * 04 Dec 2019 AE Team The first version
14 *
15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
16 *
17 * SPDX-License-Identifier: Apache-2.0
18 *
19 * Licensed under the Apache License, Version 2.0 (the License); you may
20 * not use this file except in compliance with the License.
21 * You may obtain a copy of the License at
22 *
23 * www.apache.org/licenses/LICENSE-2.0
24 *
25 * Unless required by applicable law or agreed to in writing, software
26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
28 * See the License for the specific language governing permissions and
29 * limitations under the License.
30 **********************************************************************************
31 */
32
33 #ifndef __ALD_PMU_H__
34 #define __ALD_PMU_H__
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include "utils.h"
41 #include "ald_syscfg.h"
42 #include "ald_bkpc.h"
43
44
45 /** @addtogroup ES32FXXX_ALD
46 * @{
47 */
48
49 /** @addtogroup PMU
50 * @{
51 */
52
53 /** @defgroup PMU_Public_Macros PMU Public Macros
54 * @{
55 */
56 #define PMU_LPSTOP_ENABLE() \
57 do { \
58 SYSCFG_UNLOCK(); \
59 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
60 SYSCFG_LOCK(); \
61 } while (0)
62 #define PMU_LPSTOP_DISABLE() \
63 do { \
64 SYSCFG_UNLOCK(); \
65 CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
66 SYSCFG_LOCK(); \
67 } while (0)
68 #define PMU_FLASH_MODE_IDLE() \
69 do { \
70 SYSCFG_UNLOCK(); \
71 CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
72 SYSCFG_LOCK(); \
73 } while (0)
74 #define PMU_FLASH_MODE_WAIT() \
75 do { \
76 SYSCFG_UNLOCK(); \
77 SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
78 SYSCFG_LOCK(); \
79 } while (0)
80 #define PMU_MTSTOP_ENABLE() \
81 do { \
82 SYSCFG_UNLOCK(); \
83 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
84 SYSCFG_LOCK(); \
85 } while (0)
86 #define PMU_MTSTOP_DISABLE() \
87 do { \
88 SYSCFG_UNLOCK(); \
89 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
90 SYSCFG_LOCK(); \
91 } while (0)
92 #define PMU_VREF_ENABLE() \
93 do { \
94 SYSCFG_UNLOCK(); \
95 SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
96 SYSCFG_LOCK(); \
97 } while (0)
98 #define PMU_VREF_DISABLE() \
99 do { \
100 SYSCFG_UNLOCK(); \
101 CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
102 SYSCFG_LOCK(); \
103 } while (0)
104
105 #define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
106 /**
107 * @}
108 */
109
110
111 /** @defgroup PMU_Public_Types PMU Public Types
112 * @{
113 */
114 /**
115 * @brief Low power mode
116 */
117 typedef enum {
118 PMU_LP_STOP1 = 0x0U, /**< Stop1 */
119 PMU_LP_STOP2 = 0x1U, /**< Stop2 */
120 PMU_LP_STANDBY = 0x2U, /**< Standby */
121 } pmu_lp_mode_t;
122
123 /**
124 * @brief LDO_18 mode
125 */
126 typedef enum {
127 PMU_LDO_18_DRV_HIGH = 0x0U, /**< High drive */
128 PMU_LDO_18_DRV_LOW = 0x1U, /**< Low drive */
129 PMU_LDO_18_HOLD = 0x2U, /**< Hold */
130 PMU_LDO_18_OFF = 0x3U, /**< Turn off */
131 } pmu_ldo_18_mode_t;
132
133 typedef enum {
134 PMU_SR_WUF = (1U << 0), /**< WakeUp status */
135 PMU_SR_STANDBYF = (1U << 1), /**< Standby status */
136 PMU_SR_USBRDY = (1U << 2), /**< USB Readby status */
137 PMU_SR_RSTAT = (1U << 3), /**< RUN/LPRUAN status */
138 } pmu_status_t;
139
140 /**
141 * @brief LVD voltage select
142 */
143 typedef enum {
144 PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V ~ 2.25V */
145 PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V ~ 2.45V */
146 PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V ~ 2.65V */
147 PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V ~ 2.85V */
148 PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V ~ 3.05V */
149 PMU_LVD_VOL_SEL_3_2 = 0x5U, /**< 3.2V ~ 3.25V */
150 PMU_LVD_VOL_SEL_3_4 = 0x6U, /**< 3.4V ~ 3.45V */
151 PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */
152 PMU_LVD_VOL_SEL_3_8 = 0x8U, /**< 3.8V ~ 3.85V */
153 PMU_LVD_VOL_SEL_4_0 = 0x9U, /**< 4.0V ~ 4.05V */
154 PMU_LVD_VOL_SEL_4_2 = 0xAU, /**< 4.2V ~ 4.25V */
155 PMU_LVD_VOL_SEL_4_4 = 0xBU, /**< 4.4V ~ 4.45V */
156 PMU_LVD_VOL_SEL_4_6 = 0xCU, /**< 4.6V ~ 4.65V */
157 PMU_LVD_VOL_SEL_4_8 = 0xDU, /**< 4.8V ~ 4.85V */
158 PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */
159 } pmu_lvd_voltage_sel_t;
160
161 /**
162 * @brief LVD trigger mode
163 */
164 typedef enum {
165 PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */
166 PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */
167 PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */
168 PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */
169 PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */
170 } pmu_lvd_trigger_mode_t;
171
172 /**
173 * @brief LDO output voltage selest in low power mode
174 */
175 typedef enum {
176 PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, /**< 0.9V */
177 PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, /**< 1.0V */
178 PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, /**< 1.1V */
179 PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U, /**< 1.2V */
180 } pmu_ldo_lpmode_output_t;
181
182 typedef enum {
183 PMU_POWER_SRAM0 = 0x1U, /**< SRAM0 */
184 PMU_POWER_SRAM1 = 0x2U, /**< SRAM1 */
185 PMU_POWER_SRAM2 = 0x4U, /**< SRAM2 */
186 PMU_POWER_SRAM3 = 0x8U, /**< SRAM3 */
187 PMU_POWER_SRAM4 = 0x10U, /**< SRAM4 */
188 PMU_POWER_SRAM5 = 0x20U, /**< SRAM5 */
189 PMU_POWER_CAN = 0x100U, /**< CAN */
190 PMU_POWER_QSPI = 0x400U, /**< QSPI */
191 PMU_POWER_USB = 0x800U, /**< USB */
192 PMU_POWER_ROM = 0x1000U, /**< ROM */
193 } pmu_perh_power_t;
194
195 /**
196 * @}
197 */
198
199 /**
200 * @defgroup PMU_Private_Macros PMU Private Macros
201 * @{
202 */
203 #define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
204 ((x) == PMU_LP_STOP2) || \
205 ((x) == PMU_LP_STANDBY))
206 #define IS_PMU_LDO18_MODE(x) (((x) == PMU_LDO_18_DRV_HIGH) || \
207 ((x) == PMU_LDO_18_DRV_LOW) || \
208 ((x) == PMU_LDO_18_HOLD) || \
209 ((x) == PMU_LDO_18_OFF))
210 #define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \
211 ((x) == PMU_SR_STANDBYF) || \
212 ((x) == PMU_SR_USBRDY) || \
213 ((x) == PMU_SR_RSTAT))
214 #define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_2) || \
215 ((x) == PMU_LVD_VOL_SEL_2_4) || \
216 ((x) == PMU_LVD_VOL_SEL_2_6) || \
217 ((x) == PMU_LVD_VOL_SEL_2_8) || \
218 ((x) == PMU_LVD_VOL_SEL_3_0) || \
219 ((x) == PMU_LVD_VOL_SEL_3_2) || \
220 ((x) == PMU_LVD_VOL_SEL_3_4) || \
221 ((x) == PMU_LVD_VOL_SEL_3_6) || \
222 ((x) == PMU_LVD_VOL_SEL_3_8) || \
223 ((x) == PMU_LVD_VOL_SEL_4_0) || \
224 ((x) == PMU_LVD_VOL_SEL_4_2) || \
225 ((x) == PMU_LVD_VOL_SEL_4_4) || \
226 ((x) == PMU_LVD_VOL_SEL_4_6) || \
227 ((x) == PMU_LVD_VOL_SEL_4_8) || \
228 ((x) == PMU_LVD_VOL_SEL_EXT))
229 #define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
230 ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
231 ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
232 ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
233 ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
234 #define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \
235 ((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \
236 ((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \
237 ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
238 #define IS_PMU_PERH_POWER(x) (((x) == PMU_POWER_SRAM0) || \
239 ((x) == PMU_POWER_SRAM1) || \
240 ((x) == PMU_POWER_SRAM2) || \
241 ((x) == PMU_POWER_SRAM3) || \
242 ((x) == PMU_POWER_SRAM4) || \
243 ((x) == PMU_POWER_SRAM5) || \
244 ((x) == PMU_POWER_CAN) || \
245 ((x) == PMU_POWER_QSPI) || \
246 ((x) == PMU_POWER_USB) || \
247 ((x) == PMU_POWER_ROM))
248
249 /**
250 * @}
251 */
252
253 /** @addtogroup PMU_Public_Functions
254 * @{
255 */
256 /** @addtogroup PMU_Public_Functions_Group1
257 * @{
258 */
259 /* Low power mode select */
ald_pmu_sleep()260 __STATIC_INLINE__ void ald_pmu_sleep()
261 {
262 __WFI();
263 }
264
ald_pmu_sleep_deep()265 __STATIC_INLINE__ void ald_pmu_sleep_deep()
266 {
267 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
268 __WFI();
269 }
270
271 void ald_pmu_stop1_enter(void);
272 void ald_pmu_stop2_enter(void);
273 void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
274 void ald_pmu_ldo_12_config(type_func_t state);
275 void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode);
276 #ifdef ES32F336x /* MCU Series: ES32F336x */
277 void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
278 #endif
279 flag_status_t ald_pmu_get_status(pmu_status_t sr);
280 void ald_pmu_clear_status(pmu_status_t sr);
281 void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state);
282 /**
283 * @}
284 */
285 /** @addtogroup PMU_Public_Functions_Group2
286 * @{
287 */
288 /* LVD configure */
289 void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
290 void ald_lvd_irq_handler(void);
291 /**
292 * @}
293 */
294 /**
295 * @}
296 */
297
298 /**
299 * @}
300 */
301
302 /**
303 * @}
304 */
305 #ifdef __cplusplus
306 }
307 #endif
308
309 #endif /* __ALD_PMU_H__ */
310