| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/ |
| A D | stm32l1xx_ll_pwr.h | 35 #if defined(PWR)
203 SET_BIT(PWR->CR, PWR_CR_LPRUN); in LL_PWR_EnableLowPowerRunMode()
297 SET_BIT(PWR->CR, PWR_CR_DBP); in LL_PWR_EnableBkUpAccess()
307 CLEAR_BIT(PWR->CR, PWR_CR_DBP); in LL_PWR_DisableBkUpAccess()
446 SET_BIT(PWR->CR, PWR_CR_PVDE); in LL_PWR_EnablePVD()
485 SET_BIT(PWR->CSR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
503 CLEAR_BIT(PWR->CSR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
531 SET_BIT(PWR->CR, PWR_CR_ULP); in LL_PWR_EnableUltraLowPower()
562 SET_BIT(PWR->CR, PWR_CR_FWU); in LL_PWR_EnableFastWakeUp()
664 SET_BIT(PWR->CR, PWR_CR_CSBF); in LL_PWR_ClearFlag_SB()
[all …]
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| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/ |
| A D | n32g43x_pwr.c | 144 tmpreg = PWR->CTRL1; in PWR_MRconfig()
149 PWR->CTRL1 = tmpreg; in PWR_MRconfig()
173 PWR->CTRL2 |= Cmd; in PWR_PvdEnable()
218 Temp = PWR->CTRL3; in PWR_WakeUpPinEnable()
299 tmpreg = PWR->CTRL3; in PWR_EnterSTOP2Mode()
304 PWR->CTRL3 = tmpreg; in PWR_EnterSTOP2Mode()
306 tmpreg = PWR->CTRL1; in PWR_EnterSTOP2Mode()
312 PWR->CTRL1 = tmpreg; in PWR_EnterSTOP2Mode()
314 tmpreg = PWR->CTRL3; in PWR_EnterSTOP2Mode()
316 PWR->CTRL3 = tmpreg; in PWR_EnterSTOP2Mode()
[all …]
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| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/ |
| A D | n32l40x_pwr.c | 144 tmpreg = PWR->CTRL1; in PWR_MRconfig()
149 PWR->CTRL1 = tmpreg; in PWR_MRconfig()
173 PWR->CTRL2 |= Cmd; in PWR_PvdEnable()
218 Temp = PWR->CTRL3; in PWR_WakeUpPinEnable()
223 PWR->CTRL3 = Temp; in PWR_WakeUpPinEnable()
296 tmpreg = PWR->CTRL3; in PWR_EnterSTOP2Mode()
301 PWR->CTRL3 = tmpreg; in PWR_EnterSTOP2Mode()
303 tmpreg = PWR->CTRL1; in PWR_EnterSTOP2Mode()
309 PWR->CTRL1 = tmpreg; in PWR_EnterSTOP2Mode()
354 tmpreg = PWR->CTRL1; in PWR_EnterLowPowerRunMode()
[all …]
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/ |
| A D | n32l43x_pwr.c | 144 tmpreg = PWR->CTRL1; in PWR_MRconfig()
149 PWR->CTRL1 = tmpreg; in PWR_MRconfig()
176 PWR->CTRL2 |= Cmd; in PWR_PvdEnable()
220 Temp = PWR->CTRL3; in PWR_WakeUpPinEnable()
225 PWR->CTRL3 = Temp; in PWR_WakeUpPinEnable()
293 tmpreg = PWR->CTRL3; in PWR_EnterSTOP2Mode()
298 PWR->CTRL3 = tmpreg; in PWR_EnterSTOP2Mode()
300 tmpreg = PWR->CTRL1; in PWR_EnterSTOP2Mode()
306 PWR->CTRL1 = tmpreg; in PWR_EnterSTOP2Mode()
346 tmpreg = PWR->CTRL1; in PWR_EnterLowPowerRunMode()
[all …]
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| /bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f20x_pwr.c | 85 tmpreg = PWR->CTLR; in PWR_PVDLevelConfig()
88 PWR->CTLR = tmpreg; in PWR_PVDLevelConfig()
124 tmpreg = PWR->CTLR; in PWR_EnterSTOPMode()
127 PWR->CTLR = tmpreg; in PWR_EnterSTOPMode()
212 tmpreg = PWR->CTLR; in PWR_EnterSTOPMode_RAM()
219 PWR->CTLR = tmpreg; in PWR_EnterSTOPMode_RAM()
249 tmpreg = PWR->CTLR; in PWR_EnterSTOPMode_RAM_LV()
258 PWR->CTLR = tmpreg; in PWR_EnterSTOPMode_RAM_LV()
283 tmpreg = PWR->CTLR; in PWR_EnterSTANDBYMode_RAM()
291 PWR->CTLR = tmpreg; in PWR_EnterSTANDBYMode_RAM()
[all …]
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| /bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32v10x_pwr.c | 46 PWR->CTLR |= (1 << 8); in PWR_BackupAccessCmd()
50 PWR->CTLR &= ~(1 << 8); in PWR_BackupAccessCmd()
67 PWR->CTLR |= (1 << 4); in PWR_PVDCmd()
71 PWR->CTLR &= ~(1 << 4); in PWR_PVDCmd()
96 tmpreg = PWR->CTLR; in PWR_PVDLevelConfig()
99 PWR->CTLR = tmpreg; in PWR_PVDLevelConfig()
116 PWR->CSR |= (1 << 8); in PWR_WakeUpPinCmd()
120 PWR->CSR &= ~(1 << 8); in PWR_WakeUpPinCmd()
141 tmpreg = PWR->CTLR; in PWR_EnterSTOPMode()
144 PWR->CTLR = tmpreg; in PWR_EnterSTOPMode()
[all …]
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| /bsp/mm32l07x/Libraries/MM32L0xx/HAL_lib/src/ |
| A D | HAL_pwr.c | 140 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
144 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
162 PWR->CR |= 0x00000010; in PWR_PVDCmd()
166 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
276 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
278 PWR->CR |= CR_PDDS_Set; in PWR_EnterSTANDBYMode()
[all …]
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| /bsp/mm32l3xx/Libraries/MM32L3xx/HAL_lib/src/ |
| A D | HAL_pwr.c | 139 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
143 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
161 PWR->CR |= 0x00000010; in PWR_PVDCmd()
165 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
277 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
279 PWR->CR |= CR_PDDS_Set; in PWR_EnterSTANDBYMode()
[all …]
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| /bsp/tkm32F499/Libraries/Hal_lib/src/ |
| A D | HAL_pwr.c | 139 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
143 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
161 PWR->CR |= 0x00000010; in PWR_PVDCmd()
165 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
215 PWR->CSR |= 0x00000100; in PWR_WakeUpPinCmd()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
277 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
[all …]
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| /bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/ |
| A D | HAL_pwr.c | 139 PWR->CR |= 0x00000100; in PWR_BackupAccessCmd()
143 PWR->CR &= 0xfffffeff; in PWR_BackupAccessCmd()
161 PWR->CR |= 0x00000010; in PWR_PVDCmd()
165 PWR->CR &= 0xffffffef; in PWR_PVDCmd()
193 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
199 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
245 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
251 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
277 PWR->CR |= CR_CWUF_Set; in PWR_EnterSTANDBYMode()
279 PWR->CR |= CR_PDDS_Set; in PWR_EnterSTANDBYMode()
[all …]
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| /bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ |
| A D | ft32f0xx_pwr.c | 56 PWR->CR |= PWR_CR_DBP; in PWR_BackupAccessCmd()
61 PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); in PWR_BackupAccessCmd()
101 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
110 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
127 PWR->CR |= PWR_CR_PVDE; in PWR_PVDCmd()
164 PWR->CSR |= PWR_WakeUpPin; in PWR_WakeUpPinCmd()
169 PWR->CSR &= ~PWR_WakeUpPin; in PWR_WakeUpPinCmd()
238 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
246 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
287 PWR->CR |= PWR_CR_PDDS; in PWR_EnterSTANDBYMode()
[all …]
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| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/src/ |
| A D | hk32f0xx_pwr.c | 83 PWR->CR |= PWR_CR_DBP; in PWR_BackupAccessCmd()
139 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
148 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
165 PWR->CR |= PWR_CR_PVDE; in PWR_PVDCmd()
213 PWR->CSR |= PWR_WakeUpPin; in PWR_WakeUpPinCmd()
218 PWR->CSR &= ~PWR_WakeUpPin; in PWR_WakeUpPinCmd()
392 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
421 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
465 PWR->CR |= PWR_CR_PDDS; in PWR_EnterSTANDBYMode()
512 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) in PWR_GetFlagStatus()
[all …]
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| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/ |
| A D | hal_pwr.c | 100 (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1); in PWR_WakeUpPinCmd()
111 … (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin)); in PWR_WakeUpPinXCmd()
130 MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator); in PWR_EnterSTOPMode()
148 PWR->CR |= PWR_CR_PDDS; in PWR_EnterSTANDBYMode()
149 …PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SC… in PWR_EnterSTANDBYMode()
181 PWR->CR |= flag << 2; in PWR_ClearPVDOFlag()
195 return (FlagStatus)(PWR->CSR & flag); in PWR_GetFlagStatus()
208 PWR->CR |= flag << 2; in PWR_ClearFlag()
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| /bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/ |
| A D | n32g4fr_pwr.c | 168 tmpregister = PWR->CTRL; in PWR_PvdRangeConfig()
174 PWR->CTRL = tmpregister; in PWR_PvdRangeConfig()
255 tmpregister = PWR->CTRL; in PWR_EnterStopState()
261 PWR->CTRL = tmpregister; in PWR_EnterStopState()
297 tmpregister = PWR->CTRL; in PWR_EnterSTOP2Mode()
301 PWR->CTRL = tmpregister; in PWR_EnterSTOP2Mode()
303 PWR->CTRL2 |= PWR_CTRL2_STOP2S; in PWR_EnterSTOP2Mode()
331 PWR->CTRL |= PWR_CTRL_CWKUP; in PWR_EnterStandbyState()
333 PWR->CTRL &= CTRL_DS_MASK; in PWR_EnterStandbyState()
335 PWR->CTRL |= PWR_CTRL_PDS; in PWR_EnterStandbyState()
[all …]
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| /bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_pwr.c | 168 tmpregister = PWR->CTRL; in PWR_PvdRangeConfig()
174 PWR->CTRL = tmpregister; in PWR_PvdRangeConfig()
255 tmpregister = PWR->CTRL; in PWR_EnterStopState()
261 PWR->CTRL = tmpregister; in PWR_EnterStopState()
297 tmpregister = PWR->CTRL; in PWR_EnterSTOP2Mode()
301 PWR->CTRL = tmpregister; in PWR_EnterSTOP2Mode()
303 PWR->CTRL2 |= PWR_CTRL2_STOP2S; in PWR_EnterSTOP2Mode()
331 PWR->CTRL |= PWR_CTRL_CWKUP; in PWR_EnterStandbyState()
333 PWR->CTRL &= CTRL_DS_MASK; in PWR_EnterStandbyState()
335 PWR->CTRL |= PWR_CTRL_PDS; in PWR_EnterStandbyState()
[all …]
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| /bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/ |
| A D | n32wb452_pwr.c | 168 tmpregister = PWR->CTRL; in PWR_PvdRangeConfig()
174 PWR->CTRL = tmpregister; in PWR_PvdRangeConfig()
255 tmpregister = PWR->CTRL; in PWR_EnterStopState()
261 PWR->CTRL = tmpregister; in PWR_EnterStopState()
297 tmpregister = PWR->CTRL; in PWR_EnterSTOP2Mode()
301 PWR->CTRL = tmpregister; in PWR_EnterSTOP2Mode()
303 PWR->CTRL2 |= PWR_CTRL2_STOP2S; in PWR_EnterSTOP2Mode()
331 PWR->CTRL |= PWR_CTRL_CWKUP; in PWR_EnterStandbyState()
333 PWR->CTRL &= CTRL_DS_MASK; in PWR_EnterStandbyState()
335 PWR->CTRL |= PWR_CTRL_PDS; in PWR_EnterStandbyState()
[all …]
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| /bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_pwr.c | 168 tmpregister = PWR->CTRL; in PWR_PvdRangeConfig()
174 PWR->CTRL = tmpregister; in PWR_PvdRangeConfig()
255 tmpregister = PWR->CTRL; in PWR_EnterStopState()
261 PWR->CTRL = tmpregister; in PWR_EnterStopState()
297 tmpregister = PWR->CTRL; in PWR_EnterSTOP2Mode()
301 PWR->CTRL = tmpregister; in PWR_EnterSTOP2Mode()
303 PWR->CTRL2 |= PWR_CTRL2_STOP2S; in PWR_EnterSTOP2Mode()
331 PWR->CTRL |= PWR_CTRL_CWKUP; in PWR_EnterStandbyState()
333 PWR->CTRL &= CTRL_DS_MASK; in PWR_EnterStandbyState()
335 PWR->CTRL |= PWR_CTRL_PDS; in PWR_EnterStandbyState()
[all …]
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| /bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ |
| A D | ch32f10x_pwr.c | 92 tmpreg = PWR->CTLR; in PWR_PVDLevelConfig()
95 PWR->CTLR = tmpreg; in PWR_PVDLevelConfig()
125 tmpreg = PWR->CTLR; in PWR_EnterSTOPMode()
128 PWR->CTLR = tmpreg; in PWR_EnterSTOPMode()
151 PWR->CTLR |= PWR_CTLR_CWUF; in PWR_EnterSTANDBYMode()
152 PWR->CTLR |= PWR_CTLR_PDDS; in PWR_EnterSTANDBYMode()
174 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) in PWR_GetFlagStatus()
196 PWR->CTLR |= PWR_FLAG << 2; in PWR_ClearFlag()
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| /bsp/airm2m/air32f103/libraries/AIR32F10xLib/src/ |
| A D | air32f10x_pwr.c | 138 tmpreg = PWR->CR; in PWR_PVDLevelConfig()
144 PWR->CR = tmpreg; in PWR_PVDLevelConfig()
180 tmpreg = PWR->CR; in PWR_EnterSTOPMode()
186 PWR->CR = tmpreg; in PWR_EnterSTOPMode()
214 PWR->CR |= PWR_CR_CWUF; in PWR_EnterSTANDBYMode()
216 PWR->CR |= PWR_CR_PDDS; in PWR_EnterSTANDBYMode()
242 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) in PWR_GetFlagStatus()
267 PWR->CR |= PWR_FLAG << 2; in PWR_ClearFlag()
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/ |
| A D | n32l43x_pwr.h | 182 #define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <…
183 #define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<…
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| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/ |
| A D | n32g43x_pwr.h | 182 #define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <…
183 #define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<…
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| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/ |
| A D | stm32l1xx_hal_pwr.c | 346 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); in HAL_PWR_ConfigPVD()
453 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); in HAL_PWR_EnterSLEEPMode()
499 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); in HAL_PWR_EnterSTOPMode()
535 SET_BIT(PWR->CR, PWR_CR_PDDS); in HAL_PWR_EnterSTANDBYMode()
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| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/ |
| A D | n32l40x_pwr.h | 183 #define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <…
184 #define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<…
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| /bsp/tkm32F499/Libraries/CMSIS_and_startup/ |
| A D | sys.c | 79 PWR->CSR|=1<<8; //设置WKUP用于唤醒 in Sys_Standby()
80 PWR->CR|=1<<2; //清除Wake-up 标志 in Sys_Standby()
81 PWR->CR|=1<<1; //PDDS置位 in Sys_Standby()
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| /bsp/stm32/libraries/templates/stm32h7xx/board/ |
| A D | board.c | 21 MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0); in SystemClock_Config()
26 while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) in SystemClock_Config()
|