| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/ |
| A D | stm32l1xx_hal_cryp.c | 201 hcryp->Phase = HAL_CRYP_PHASE_READY; in HAL_CRYP_Init()
235 hcryp->Phase = HAL_CRYP_PHASE_READY; in HAL_CRYP_DeInit()
343 if(hcryp->Phase == HAL_CRYP_PHASE_READY) in HAL_CRYP_AESECB_Encrypt()
358 hcryp->Phase = HAL_CRYP_PHASE_PROCESS; in HAL_CRYP_AESECB_Encrypt()
419 if(hcryp->Phase == HAL_CRYP_PHASE_READY) in HAL_CRYP_AESCBC_Encrypt()
437 hcryp->Phase = HAL_CRYP_PHASE_PROCESS; in HAL_CRYP_AESCBC_Encrypt()
498 if(hcryp->Phase == HAL_CRYP_PHASE_READY) in HAL_CRYP_AESCTR_Encrypt()
516 hcryp->Phase = HAL_CRYP_PHASE_PROCESS; in HAL_CRYP_AESCTR_Encrypt()
577 if(hcryp->Phase == HAL_CRYP_PHASE_READY) in HAL_CRYP_AESECB_Decrypt()
592 hcryp->Phase = HAL_CRYP_PHASE_PROCESS; in HAL_CRYP_AESECB_Decrypt()
[all …]
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/ |
| A D | n32l43x_usart.c | 289 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
302 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
317 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/ |
| A D | n32l40x_usart.c | 289 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
302 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
317 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/ |
| A D | n32g43x_usart.c | 289 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
302 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
317 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/ |
| A D | n32g4fr_usart.c | 307 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
320 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
335 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_usart.c | 307 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
320 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
335 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/ |
| A D | n32wb452_usart.c | 307 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
320 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
335 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/ |
| A D | n32g45x_usart.c | 302 assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase)); in USART_ClockInit()
315 | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; in USART_ClockInit()
330 USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; in USART_ClockStructInit()
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| /bsp/microchip/saml10/bsp/ |
| A D | atmel_start_config.atstart | 250 $input_id: Digital Phase Locked Loop (DPLL)
252 RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL)
295 gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL)
384 _$freq_output_Digital Phase Locked Loop (DPLL): 32000000
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| /bsp/microchip/samc21/ |
| A D | README_zh.md | 24 …- Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (…
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| A D | README.md | 24 …- Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (…
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| /bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/ |
| A D | stm32l1xx_hal_cryp.h | 103 HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ member
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| A D | stm32l1xx_ll_usart.h | 749 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity,… in LL_USART_ConfigClock() argument
751 …MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPO… in LL_USART_ConfigClock()
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| /bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/ |
| A D | n32l43x_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/ |
| A D | n32wb452_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/ |
| A D | n32l40x_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/ |
| A D | n32g4fr_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/ |
| A D | n32g43x_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/ |
| A D | n32g45x_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/ |
| A D | n32g45x_usart.h | 100 uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made. member
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| /bsp/ti/c28x/tms320f28379d/board/ |
| A D | Kconfig | 131 int "Phase, 0~360"
351 int "Phase, 0~360"
571 int "Phase, 0~360"
791 int "Phase, 0~360"
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| /bsp/microchip/saml10/ |
| A D | README.md | 41 - 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
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| A D | README_zh.md | 41 - 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
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| /bsp/microchip/same54/bsp/ |
| A D | atmel_start_config.atstart | 767 gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0)
782 gclk_gen_3_oscillator: Digital Phase Locked Loop (DPLL0)
877 _$freq_output_Digital Phase Locked Loop (DPLL0): 120000000
878 _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664
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| /bsp/microchip/samc21/bsp/ |
| A D | atmel_start_config.atstart | 458 gclk_gen_0_oscillator: Fractional Digital Phase Locked Loop (FDPLL96M)
575 _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 40001536
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