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Searched refs:Pm (Results 1 – 25 of 97) sorted by relevance

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/bsp/microchip/saml10/bsp/hri/
A Dhri_pm_l10.h83 tmp = ((Pm *)hw)->INTFLAG.reg; in hri_pm_get_INTFLAG_reg()
250 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_get_PLCFG_PLDIS_bit()
259 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_write_PLCFG_PLDIS_bit()
262 ((Pm *)hw)->PLCFG.reg = tmp; in hri_pm_write_PLCFG_PLDIS_bit()
290 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_get_PLCFG_PLSEL_bf()
299 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_write_PLCFG_PLSEL_bf()
302 ((Pm *)hw)->PLCFG.reg = tmp; in hri_pm_write_PLCFG_PLSEL_bf()
323 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_read_PLCFG_PLSEL_bf()
338 tmp = ((Pm *)hw)->PLCFG.reg; in hri_pm_get_PLCFG_reg()
379 tmp = ((Pm *)hw)->PWCFG.reg; in hri_pm_get_PWCFG_RAMPSWC_bf()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_pm_e54.h85 tmp = ((Pm *)hw)->INTFLAG.reg; in hri_pm_get_INTFLAG_reg()
92 return ((Pm *)hw)->INTFLAG.reg; in hri_pm_read_INTFLAG_reg()
97 ((Pm *)hw)->INTFLAG.reg = mask; in hri_pm_clear_INTFLAG_reg()
163 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_IORET_bit()
172 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_write_CTRLA_IORET_bit()
175 ((Pm *)hw)->CTRLA.reg = tmp; in hri_pm_write_CTRLA_IORET_bit()
196 ((Pm *)hw)->CTRLA.reg |= mask; in hri_pm_set_CTRLA_reg()
203 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_reg()
211 ((Pm *)hw)->CTRLA.reg = data; in hri_pm_write_CTRLA_reg()
225 ((Pm *)hw)->CTRLA.reg ^= mask; in hri_pm_toggle_CTRLA_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_pm_d51.h85 tmp = ((Pm *)hw)->INTFLAG.reg; in hri_pm_get_INTFLAG_reg()
92 return ((Pm *)hw)->INTFLAG.reg; in hri_pm_read_INTFLAG_reg()
97 ((Pm *)hw)->INTFLAG.reg = mask; in hri_pm_clear_INTFLAG_reg()
163 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_IORET_bit()
172 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_write_CTRLA_IORET_bit()
175 ((Pm *)hw)->CTRLA.reg = tmp; in hri_pm_write_CTRLA_IORET_bit()
196 ((Pm *)hw)->CTRLA.reg |= mask; in hri_pm_set_CTRLA_reg()
203 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_reg()
211 ((Pm *)hw)->CTRLA.reg = data; in hri_pm_write_CTRLA_reg()
225 ((Pm *)hw)->CTRLA.reg ^= mask; in hri_pm_toggle_CTRLA_reg()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_pm_d51.h85 tmp = ((Pm *)hw)->INTFLAG.reg; in hri_pm_get_INTFLAG_reg()
92 return ((Pm *)hw)->INTFLAG.reg; in hri_pm_read_INTFLAG_reg()
97 ((Pm *)hw)->INTFLAG.reg = mask; in hri_pm_clear_INTFLAG_reg()
163 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_IORET_bit()
172 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_write_CTRLA_IORET_bit()
175 ((Pm *)hw)->CTRLA.reg = tmp; in hri_pm_write_CTRLA_IORET_bit()
196 ((Pm *)hw)->CTRLA.reg |= mask; in hri_pm_set_CTRLA_reg()
203 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_reg()
211 ((Pm *)hw)->CTRLA.reg = data; in hri_pm_write_CTRLA_reg()
225 ((Pm *)hw)->CTRLA.reg ^= mask; in hri_pm_toggle_CTRLA_reg()
[all …]
/bsp/microchip/samc21/bsp/hri/
A Dhri_pm_c21.h66 tmp = ((Pm *)hw)->SLEEPCFG.reg; in hri_pm_get_SLEEPCFG_SLEEPMODE_bf()
75 tmp = ((Pm *)hw)->SLEEPCFG.reg; in hri_pm_write_SLEEPCFG_SLEEPMODE_bf()
78 ((Pm *)hw)->SLEEPCFG.reg = tmp; in hri_pm_write_SLEEPCFG_SLEEPMODE_bf()
99 tmp = ((Pm *)hw)->SLEEPCFG.reg; in hri_pm_read_SLEEPCFG_SLEEPMODE_bf()
114 tmp = ((Pm *)hw)->SLEEPCFG.reg; in hri_pm_get_SLEEPCFG_reg()
155 tmp = ((Pm *)hw)->STDBYCFG.reg; in hri_pm_get_STDBYCFG_BBIASHS_bit()
164 tmp = ((Pm *)hw)->STDBYCFG.reg; in hri_pm_write_STDBYCFG_BBIASHS_bit()
167 ((Pm *)hw)->STDBYCFG.reg = tmp; in hri_pm_write_STDBYCFG_BBIASHS_bit()
195 tmp = ((Pm *)hw)->STDBYCFG.reg; in hri_pm_get_STDBYCFG_VREGSMOD_bf()
204 tmp = ((Pm *)hw)->STDBYCFG.reg; in hri_pm_write_STDBYCFG_VREGSMOD_bf()
[all …]
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dpm.h107 } Pm; typedef
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dpm.h256 } Pm; typedef
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dpm.h256 } Pm; typedef
/bsp/microchip/same54/bsp/include/component/
A Dpm.h256 } Pm; typedef
/bsp/microchip/saml10/bsp/include/component/
A Dpm.h260 } Pm; typedef
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/
A Dsamd20e14.h420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20e15.h420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g14.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g15.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g16.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g17.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g17u.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g18.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20g18u.h427 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20e16.h420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20e17.h420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20e18.h420 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20j14.h440 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20j15.h440 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
A Dsamd20j16.h440 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */

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