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/bsp/yichip/yc3121-pos/drivers/linker_scripts/
A Dlink.lds5 * RAM.ORIGIN: starting address of RAM bank 0
6 * RAM.LENGTH: length of RAM bank 0
11 RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */
15 * with other linker script that defines memory regions FLASH and RAM.
125 } > RAM
135 } > RAM
143 } > RAM
151 } > RAM
153 /* Set stack top to end of RAM, and stack limit move down by
155 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
[all …]
/bsp/yichip/yc3122-pos/drivers/linker_scripts/
A Dlink.lds5 * RAM.ORIGIN: starting address of RAM bank 0
6 * RAM.LENGTH: length of RAM bank 0
11 RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */
15 * with other linker script that defines memory regions FLASH and RAM.
125 } > RAM
135 } > RAM
143 } > RAM
151 } > RAM
153 /* Set stack top to end of RAM, and stack limit move down by
155 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
[all …]
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/GCC/
A Defm32g.ld5 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16384
9 * with other linker script that defines memory regions FLASH and RAM.
111 } > RAM
119 } > RAM
128 } > RAM
136 } > RAM
138 /* Set stack top to end of RAM, and stack limit move down by
140 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
144 /* Check if data + heap + stack exceeds RAM limit */
145 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/GCC/
A Defm32gg.ld5 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 131072
9 * with other linker script that defines memory regions FLASH and RAM.
111 } > RAM
119 } > RAM
128 } > RAM
136 } > RAM
138 /* Set stack top to end of RAM, and stack limit move down by
140 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
144 /* Check if data + heap + stack exceeds RAM limit */
145 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/frdm-k64f/
A DK64FN1M0xxx12.ld10 RAM (rwx) : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198
14 * with other linker script that defines memory regions FLASH and RAM.
149 } > RAM
157 } > RAM
165 } > RAM
173 } > RAM
175 /* Set stack top to end of RAM, and stack limit move down by
177 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
181 /* Check if data + heap + stack exceeds RAM limit */
182 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/efm32/
A Defm32g_rom.ld17 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16384
22 * with other linker script that defines memory regions FLASH and RAM.
141 } > RAM
149 } > RAM
158 } > RAM
166 } > RAM
168 /* Set stack top to end of RAM, and stack limit move down by
170 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
174 /* Check if data + heap + stack exceeds RAM limit */
175 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
A Defm32gg_rom.ld15 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 131072
20 * with other linker script that defines memory regions FLASH and RAM.
132 } > RAM
140 } > RAM
149 } > RAM
157 } > RAM
159 /* Set stack top to end of RAM, and stack limit move down by
161 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
165 /* Check if data + heap + stack exceeds RAM limit */
166 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/nrf5x/nrf51822/board/linker_scripts/
A Dlink.lds9 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
113 } > RAM
123 } > RAM
132 } > RAM
140 } > RAM
142 /* Set stack top to end of RAM, and stack limit move down by
144 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
148 /* Check if data + heap + stack exceeds RAM limit */
149 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/nrf5x/nrf52840/board/linker_scripts/
A Dlink.lds9 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
113 } > RAM
123 } > RAM
132 } > RAM
140 } > RAM
142 /* Set stack top to end of RAM, and stack limit move down by
144 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
148 /* Check if data + heap + stack exceeds RAM limit */
149 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/nrf5x/nrf5340/board/linker_scripts/
A Dlink.lds9 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x80000
120 } > RAM
130 } > RAM
139 } > RAM
147 } > RAM
149 /* Set stack top to end of RAM, and stack limit move down by
151 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
155 /* Check if data + heap + stack exceeds RAM limit */
156 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/nrf5x/nrf52833/board/linker_scripts/
A Dlink.lds9 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000
113 } > RAM
123 } > RAM
132 } > RAM
140 } > RAM
142 /* Set stack top to end of RAM, and stack limit move down by
144 __StackTop = ORIGIN(RAM) + LENGTH(RAM);
148 /* Check if data + heap + stack exceeds RAM limit */
149 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Source/GCC/
A Dgcc_arm.ld39 <h> RAM Configuration
40 <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
41 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
67 * with other linker script that defines memory regions FLASH and RAM.
219 } > RAM
252 } > RAM AT > RAM
281 } > RAM
283 .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :
290 } > RAM
[all …]
/bsp/w60x/drivers/linker_scripts/
A Dlink.lds5 * RAM.ORIGIN: starting address of RAM bank 0
6 * RAM.LENGTH: length of RAM bank 0
12 RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x28000 /* 160K */
17 * with other linker script that defines memory regions FLASH and RAM.
158 } > RAM
166 } > RAM
183 } > RAM
/bsp/tae32f5300/board/linker_scripts/
A Dlink.lds4 * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM.
26 RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
136 } >RAM
160 } >RAM
186 } >RAM
201 __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
202 ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
/bsp/hc32l136/board/linker_scripts/
A Dlink.lds4 * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM.
26 RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
136 } >RAM
160 } >RAM
186 } >RAM
201 __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
202 ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
/bsp/apm32/libraries/APM32E10x_Library/Device/Geehy/APM32E10x/Source/gcc/
A Dgcc_APM32E10xxC.ld5 * 256KByte FLASH, 64KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
143 } >RAM
153 } >RAM
A Dgcc_APM32E10xxE.ld5 * 512KByte FLASH, 128KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
143 } >RAM
153 } >RAM
/bsp/apm32/libraries/APM32F0xx_Library/Device/Geehy/APM32F0xx/Source/gcc/
A Dgcc_APM32F03xx6.ld5 * 32KByte FLASH, 4KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F03xx8.ld5 * 64KByte FLASH, 8KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F03xxC.ld5 * 256KByte FLASH, 32KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F05xx6.ld5 * 32KByte FLASH, 8KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F05xx8.ld5 * 64KByte FLASH, 8KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F07xx8.ld5 * 64KByte FLASH, 16KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F07xxB.ld5 * 128KByte FLASH, 32KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM
A Dgcc_APM32F09xxB.ld5 * 128KByte FLASH, 32KByte RAM
36 /* Embedded RAM Configuration */
37 /* RAM Base Address */
39 /* RAM Size (in Bytes) */
52 RAM (xrw) : ORIGIN = _ram_base, LENGTH = _ram_size
127 } >RAM AT> FLASH
142 } >RAM
152 } >RAM

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