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Searched refs:RB_CLK_SYS_MOD (Results 1 – 2 of 2) sorted by relevance

/bsp/wch/arm/ch579m/libraries/StdPeriphDriver/
A DCH57x_clk.c125 if( (rev & RB_CLK_SYS_MOD) == (2<<6) ){ // 32M做主频 in GetSysClock()
128 else if( (rev & RB_CLK_SYS_MOD) == (1<<6) ){ // PLL进行分频 in GetSysClock()
131 else if( (rev & RB_CLK_SYS_MOD) == (0<<6) ){ // 32M进行分频 in GetSysClock()
273 if( (rev & RB_CLK_SYS_MOD) == (2<<6) ){ // 32M做主频 in Calibration_LSI()
277 else if( (rev & RB_CLK_SYS_MOD) == (1<<6) ){ // PLL进行分频 in Calibration_LSI()
281 else if( (rev & RB_CLK_SYS_MOD) == (0<<6) ){ // 32M进行分频 in Calibration_LSI()
/bsp/wch/arm/ch579m/libraries/StdPeriphDriver/inc/
A DCH579SFR.h247 #define RB_CLK_SYS_MOD 0xC0 // RWA, system clock source mode: 00=divided … macro

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