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Searched refs:RCC_CSR_IWDGRSTF_Pos (Results 1 – 25 of 28) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_rcc.h547 #define RCC_CSR_IWDGRSTF_Pos (29) macro
548 #define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Wa…
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Inc/
A Dhal_rcc.h90 …RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watch…
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_rcc.h617 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) …
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h3340 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
3341 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dhk32f031x4x6.h3386 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
3387 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dhk32f04ax4x6x8.h3332 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
3333 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h4502 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4503 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l100xba.h4529 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4530 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xb.h4387 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4388 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xba.h4417 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4418 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xb.h4529 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4530 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xba.h4544 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4545 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l100xc.h4649 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4650 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l162xdx.h5091 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
5092 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l162xe.h5091 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
5092 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xc.h4832 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4833 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xca.h4887 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4888 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xe.h4952 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4953 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l162xc.h4971 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4972 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l162xca.h5026 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
5027 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xca.h4745 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4746 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xdx.h4810 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4811 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xe.h4810 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4811 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l151xc.h4690 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4691 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
A Dstm32l152xdx.h4952 #define RCC_CSR_IWDGRSTF_Pos (29U) macro
4953 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */

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