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Searched refs:RCC_CSR_WWDGRSTF_Pos (Results 1 – 25 of 28) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_rcc.h550 #define RCC_CSR_WWDGRSTF_Pos (30) macro
551 #define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdo…
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Inc/
A Dhal_rcc.h91 …RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog r…
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_rcc.h618 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) …
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h3343 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
3344 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dhk32f031x4x6.h3389 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
3390 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dhk32f04ax4x6x8.h3335 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
3336 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h4505 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4506 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l100xba.h4532 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4533 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xb.h4390 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4391 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xba.h4420 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4421 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xb.h4532 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4533 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xba.h4547 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4548 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l100xc.h4652 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4653 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l162xdx.h5094 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
5095 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l162xe.h5094 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
5095 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xc.h4835 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4836 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xca.h4890 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4891 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xe.h4955 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4956 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l162xc.h4974 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4975 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l162xca.h5029 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
5030 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xca.h4748 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4749 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xdx.h4813 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4814 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xe.h4813 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4814 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l151xc.h4693 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4694 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
A Dstm32l152xdx.h4955 #define RCC_CSR_WWDGRSTF_Pos (30U) macro
4956 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */

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