RCC_PLLCFGR_PLL_DN (reference) in projects: bsp

Searched refs:RCC_PLLCFGR_PLL_DN (Results 1 – 3 of 3) sorted by relevance

/bsp/mm32f327x/Libraries/MM32F327x/Source/
A D	system_mm32f327x.c	386 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo24() 459 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo36() 532 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo48() 635 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockToXX() 679 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo24_HSI() 712 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo36_HSI() 749 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockTo48_HSI() 822 RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); in SetSysClockToXX_HSI()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A D	hal_rcc.c	`51 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN \| RCC_PLLCFGR_PLL_DP); in RCC_DeInit() 194 …MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN \| RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_… in RCC_PLLDMDNConfig() 426 mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1; in RCC_GetSysClockFreq()`
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A D	reg_rcc.h	`630 #define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider f… macro`

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