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Searched refs:RCC_PLLCFGR_PLL_DN_Pos (Results 1 – 3 of 3) sorted by relevance

/bsp/mm32f327x/Libraries/MM32F327x/Source/
A Dsystem_mm32f327x.c387 RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo24()
460 RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo36()
533 RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo48()
636 RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockToXX()
680 RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo24_HSI()
713 RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo36_HSI()
750 RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockTo48_HSI()
823 RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); in SetSysClockToXX_HSI()
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_rcc.h629 #define RCC_PLLCFGR_PLL_DN_Pos (16) macro
630 #define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider f…
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_rcc.c194 …->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm … in RCC_PLLDMDNConfig()
426 mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1; in RCC_GetSysClockFreq()

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