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Searched refs:READ_REG (Results 1 – 25 of 125) sorted by relevance

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/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_calc.c70 return READ_REG(CALC->SQRTRES); in ald_calc_sqrt()
89 *remainder = READ_REG(CALC->DIVRR); in ald_calc_div()
90 return READ_REG(CALC->DIVQR); in ald_calc_div()
109 *remainder = READ_REG(CALC->DIVRR); in ald_calc_div_sign()
110 return READ_REG(CALC->DIVQR); in ald_calc_div_sign()
A Dald_gpio.c206 tmp = READ_REG(GPIOx->MODE); in ald_gpio_init()
212 tmp = READ_REG(GPIOx->ODOS); in ald_gpio_init()
218 tmp = READ_REG(GPIOx->PUPD); in ald_gpio_init()
224 tmp = READ_REG(GPIOx->ODRV); in ald_gpio_init()
234 tmp = READ_REG(GPIOx->FLT); in ald_gpio_init()
240 tmp = READ_REG(GPIOx->TYPE); in ald_gpio_init()
248 tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); in ald_gpio_init()
453 tmp = READ_REG(GPIOx->MODE); in ald_gpio_toggle_dir()
502 return READ_REG(GPIOx->DIN); in ald_gpio_read_port()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pwm.c108 uint32_t status = READ_REG(pPWM->pReg->INTSTS); in HAL_PWM_IRQHandler()
121 pPWM->result[i].period = READ_REG(PWM_PERIOD_REG(pPWM, i)); in HAL_PWM_IRQHandler()
123 pPWM->result[i].period = READ_REG(PWM_DUTY_REG(pPWM, i)); in HAL_PWM_IRQHandler()
155 ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_SetConfig()
194 ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_SetOneshot()
218 ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_SetCapturedFreq()
282 ctrl = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_GetMode()
305 intEnable = READ_REG(pPWM->pReg->INT_EN); in HAL_PWM_Enable()
311 enableConf = READ_REG(PWM_CTRL_REG(pPWM, channel)); in HAL_PWM_Enable()
336 intEnable = READ_REG(pPWM->pReg->INT_EN); in HAL_PWM_Disable()
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A Dhal_dwdma.c70 READ_REG(dwc->creg->SAR), READ_REG(dwc->creg->DAR), in DWC_DumpRegs()
71 READ_REG(dwc->creg->LLP), READ_REG(dwc->creg->CTL_HI), in DWC_DumpRegs()
72 READ_REG(dwc->creg->CTL_LO)); in DWC_DumpRegs()
176 while (READ_REG(reg->DMACFGREG) & DW_CFG_DMA_EN) { in DWDMA_off()
296 return READ_REG(dw->pReg->RAW.BLOCK); in HAL_DWDMA_GetRawBlockStatus()
308 return READ_REG(dw->pReg->RAW.ERR); in HAL_DWDMA_GetRawErrStatus()
320 return READ_REG(dw->pReg->RAW.TFR); in HAL_DWDMA_GetRawXferStatus()
461 if (READ_REG(reg->CHENREG) & dwc->mask) { in HAL_DWDMA_Start()
539 statusBlock = READ_REG(dw->pReg->RAW.BLOCK); in HAL_DWDMA_HandleChan()
540 statusXfer = READ_REG(dw->pReg->RAW.TFR); in HAL_DWDMA_HandleChan()
[all …]
A Dhal_pl330.c1175 crdn = READ_REG(reg->CRDN); in PL330_Read_Config()
1176 cr = READ_REG(reg->CR[0]); in PL330_Read_Config()
1186 pcfg->periNs = READ_REG(reg->CR[4]); in PL330_Read_Config()
1198 pcfg->irqNs = READ_REG(reg->CR[3]); in PL330_Read_Config()
1324 while ((READ_REG(reg->DSR) & PL330_DS_DMA_STATUS) != in PL330_Exec_DMAGO()
1379 return READ_REG(reg->EVENT_RIS); in HAL_PL330_GetRawIrqStatus()
1600 val = READ_REG(reg->FSRD) & 0x1; in HAL_PL330_IrqHandler()
1606 HAL_DBG("Fault PC 0x%lx\n", READ_REG(reg->DPC)); in HAL_PL330_IrqHandler()
1619 i, READ_REG(reg->FTR[i])); in HAL_PL330_IrqHandler()
1629 val = READ_REG(reg->EVENT_RIS); in HAL_PL330_IrqHandler()
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/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_gpio.c208 tmp = READ_REG(GPIOx->MODE); in ald_gpio_init()
214 tmp = READ_REG(GPIOx->ODOS); in ald_gpio_init()
220 tmp = READ_REG(GPIOx->PUPD); in ald_gpio_init()
226 tmp = READ_REG(GPIOx->PODRV); in ald_gpio_init()
232 tmp = READ_REG(GPIOx->NODRV); in ald_gpio_init()
242 tmp = READ_REG(GPIOx->FLT); in ald_gpio_init()
248 tmp = READ_REG(GPIOx->TYPE); in ald_gpio_init()
256 tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); in ald_gpio_init()
462 tmp = READ_REG(GPIOx->MODE); in ald_gpio_toggle_dir()
511 return READ_REG(GPIOx->DIN); in ald_gpio_read_port()
A Dald_qspi.c411 tmp = READ_REG(hperh->perh->DSCR); in ald_qspi_indac_transmit_by_it()
463 tmp = READ_REG(hperh->perh->SPR); in ald_qspi_indac_transmit_by_poll()
479 tmp = READ_REG(hperh->perh->SFLR); in ald_qspi_indac_transmit_by_poll()
489 tmp = READ_REG(hperh->perh->IWTR); in ald_qspi_indac_transmit_by_poll()
527 tmp = READ_REG(hperh->perh->SFLR); in ald_qspi_indac_read_by_poll()
536 tmp = READ_REG(hperh->perh->SFLR); in ald_qspi_indac_read_by_poll()
545 tmp = READ_REG(hperh->perh->SFLR); in ald_qspi_indac_read_by_poll()
555 tmp = READ_REG(hperh->perh->IRTR); in ald_qspi_indac_read_by_poll()
920 regs = READ_REG(hperh->perh->DSCR); in ald_qspi_irq_handler()
955 tmp = READ_REG(hperh->perh->SFLR); in ald_qspi_irq_handler()
[all …]
/bsp/rockchip/common/rk_hal/lib/hal/src/cru/
A Dhal_cru.c315 fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); in HAL_CRU_GetPllFreq()
316 postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset1))); in HAL_CRU_GetPllFreq()
317 postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); in HAL_CRU_GetPllFreq()
318 refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); in HAL_CRU_GetPllFreq()
319 dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset3))); in HAL_CRU_GetPllFreq()
320 frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); in HAL_CRU_GetPllFreq()
477 postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0))); in HAL_CRU_GetPllFreq()
478 fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); in HAL_CRU_GetPllFreq()
480 refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); in HAL_CRU_GetPllFreq()
481 dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1))); in HAL_CRU_GetPllFreq()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_utils.h169 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); in LL_GetUID_Word0()
178 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U)))); in LL_GetUID_Word1()
187 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U)))); in LL_GetUID_Word2()
202 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); in LL_GetFlashSize()
A Dstm32l1xx_ll_crc.h80 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
141 return (uint32_t)(READ_REG(CRCx->DR)); in LL_CRC_ReadData32()
153 return (uint32_t)(READ_REG(CRCx->IDR)); in LL_CRC_Read_IDR()
A Dstm32l1xx_ll_iwdg.h116 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
213 return (READ_REG(IWDGx->PR)); in LL_IWDG_GetPrescaler()
236 return (READ_REG(IWDGx->RLR)); in LL_IWDG_GetReloadCounter()
A Dstm32l1xx_ll_gpio.h226 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
715 temp = READ_REG(GPIOx->LCKR); in LL_GPIO_LockPin()
775 return (uint32_t)(READ_REG(GPIOx->IDR)); in LL_GPIO_ReadInputPort()
827 return (uint32_t)(READ_REG(GPIOx->ODR)); in LL_GPIO_ReadOutputPort()
948 uint32_t odr = READ_REG(GPIOx->ODR); in LL_GPIO_TogglePin()
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_gpio.c204 tmp = READ_REG(GPIOx->MODE); in ald_gpio_init()
210 tmp = READ_REG(GPIOx->OD); in ald_gpio_init()
216 tmp = READ_REG(GPIOx->PUPD); in ald_gpio_init()
222 tmp = READ_REG(GPIOx->ODRV); in ald_gpio_init()
232 tmp = READ_REG(GPIOx->FLT); in ald_gpio_init()
238 tmp = READ_REG(GPIOx->TYPE); in ald_gpio_init()
246 tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); in ald_gpio_init()
442 tmp = READ_REG(GPIOx->MODE); in ald_gpio_toggle_dir()
491 return READ_REG(GPIOx->DIN); in ald_gpio_read_port()
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_ver.c102 return(READ_REG(*((vu32*)UID_BASE))); in Get_ChipsetUIDw0()
111 return(READ_REG(*((vu32*)(UID_BASE + 4U)))); in Get_ChipsetUIDw1()
120 return(READ_REG(*((vu32*)(UID_BASE + 8U)))); in Get_ChipsetUIDw2()
A Dhal_spi.c209 templen = READ_REG(spi->ECR); in SPI_SendData()
234 temp = READ_REG(spi->RDR); in SPI_ReceiveData()
236 templen = READ_REG(spi->ECR); in SPI_ReceiveData()
240 temp |= (u32)(READ_REG(spi->RDR) << 8); in SPI_ReceiveData()
242 temp |= (u32)(READ_REG(spi->RDR) << 16); in SPI_ReceiveData()
244 temp |= (u32)(READ_REG(spi->RDR) << 24); in SPI_ReceiveData()
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dfm33xx.h91 #define READ_REG(REG) ((REG)) macro
93 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dfm33xx.h91 #define READ_REG(REG) ((REG)) macro
93 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_def.h51 #define READ_REG(REG) ((REG)) macro
52 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal.c457 return(READ_REG(*((uint32_t *)UID_BASE))); in HAL_GetUIDw0()
466 return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U)))); in HAL_GetUIDw1()
475 return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U)))); in HAL_GetUIDw2()
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dft32f0xx.h89 #define READ_REG(REG) ((REG)) macro
91 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/
A Dnu_miscutil.h32 #define READ_REG(REG) ((REG)) macro
33 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_tmr.h555 #define __LL_TMR_GET_PRESCALER(__INSTANCE__) READ_REG((__INSTANCE__)->PSCR)
570 #define __LL_TMR_GET_START_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CSVR)
585 #define __LL_TMR_GET_END_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CEVR)
600 #define __LL_TMR_GET_COUNTER(__INSTANCE__) READ_REG((__INSTANCE__)->CNTR)
628 #define __LL_TMR_GET_CAPTURE(__INSTANCE__) READ_REG((__INSTANCE__)->CCR)
/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/
A Dhc32l196_ddl.h89 #define READ_REG(REG) ((REG)) macro
91 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f0xx.h118 #define READ_REG(REG) ((REG)) macro
120 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |…
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dtypes.h98 #define READ_REG(reg) ((reg)) macro
99 #define MODIFY_REG(reg, CLEARMASK, SETMASK) WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) |…

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