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Searched refs:REG (Results 1 – 25 of 114) sorted by relevance

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/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l1xx.h204 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
206 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
208 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
210 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
212 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
214 #define READ_REG(REG) ((REG)) argument
216 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
220 #define ATOMIC_SET_BIT(REG, BIT) \ argument
224 val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
225 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
[all …]
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dfm33xx.h81 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
83 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
85 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
87 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
89 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
91 #define READ_REG(REG) ((REG)) argument
93 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dfm33xx.h81 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
83 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
85 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
87 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
89 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
91 #define READ_REG(REG) ((REG)) argument
93 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_def.h46 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
47 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
48 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
49 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
50 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
51 #define READ_REG(REG) ((REG)) argument
52 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dft32f0xx.h79 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
81 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
83 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
85 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
87 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
89 #define READ_REG(REG) ((REG)) argument
91 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/nuvoton/libraries/nu_packages/NuUtils/inc/
A Dnu_miscutil.h27 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
28 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
29 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
30 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
31 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
32 #define READ_REG(REG) ((REG)) argument
33 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/inc/
A Dhc32l196_ddl.h79 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
81 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
83 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
85 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
87 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
89 #define READ_REG(REG) ((REG)) argument
91 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f0xx.h108 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
110 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
112 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
114 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
116 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
118 #define READ_REG(REG) ((REG)) argument
120 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_def.h33 #define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the reg… argument
34 #define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specif… argument
35 #define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value o… argument
36 #define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the r… argument
37 #define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the regist… argument
38 #define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the registe… argument
39 #define MODIFY_REG(REG, CLEARMASK, SETMASK) \ argument
40 …WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value…
55 #define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check … argument
56 #define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check … argument
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_def.h203 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
211 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
219 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
226 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
234 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
241 #define READ_REG(REG) ((REG)) argument
250 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | … argument
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_def.h62 #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) argument
63 #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) argument
/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/
A Dn32g45x_eth.h270 #define IS_ETH_PHY_REG(REG) ((REG) < 0x20) argument
1369 #define IS_ETH_MMC_REGISTER(REG) … argument
1370 …(((REG) == ETH_MMCCTRL) || ((REG) == ETH_MMCRXINT) || ((REG) == ETH_MMCTXINT) || ((REG) == ETH_MMC…
1371 …|| ((REG) == ETH_MMCTXINTMSK) || ((REG) == ETH_MMCTXGFASCCNT) || ((REG) == ETH_MMCTXGFAMSCCNT) …
1372 …|| ((REG) == ETH_MMCTXGFCNT) || ((REG) == ETH_MMCRXFCECNT) || ((REG) == ETH_MMCRXFAECNT) …
1373 || ((REG) == ETH_MMCRXGUFCNT))
1425 #define IS_ETH_PTP_REGISTER(REG) … argument
1426 …(((REG) == ETH_PTPTSCTRL) || ((REG) == ETH_PTPSSINC) || ((REG) == ETH_PTPSEC) || ((REG) == ETH_PTP…
1427 …|| ((REG) == ETH_PTPSECUP) || ((REG) == ETH_PTPNSUP) || ((REG) == ETH_PTPTSADD) || ((REG) == ETH_P…
1428 || ((REG) == ETH_PTPTTNS))
/bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/
A Dn32g45x_eth.h270 #define IS_ETH_PHY_REG(REG) ((REG) < 0x20) argument
1369 #define IS_ETH_MMC_REGISTER(REG) … argument
1370 …(((REG) == ETH_MMCCTRL) || ((REG) == ETH_MMCRXINT) || ((REG) == ETH_MMCTXINT) || ((REG) == ETH_MMC…
1371 …|| ((REG) == ETH_MMCTXINTMSK) || ((REG) == ETH_MMCTXGFASCCNT) || ((REG) == ETH_MMCTXGFAMSCCNT) …
1372 …|| ((REG) == ETH_MMCTXGFCNT) || ((REG) == ETH_MMCRXFCECNT) || ((REG) == ETH_MMCRXFAECNT) …
1373 || ((REG) == ETH_MMCRXGUFCNT))
1425 #define IS_ETH_PTP_REGISTER(REG) … argument
1426 …(((REG) == ETH_PTPTSCTRL) || ((REG) == ETH_PTPSSINC) || ((REG) == ETH_PTPSEC) || ((REG) == ETH_PTP…
1427 …|| ((REG) == ETH_PTPSECUP) || ((REG) == ETH_PTPNSUP) || ((REG) == ETH_PTPTSADD) || ((REG) == ETH_P…
1428 || ((REG) == ETH_PTPTTNS))
/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DACM32F0x0.h732 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
734 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
736 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
738 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
740 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
742 #define READ_REG(REG) ((REG)) argument
744 #define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) argument
/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DACM32F4.h817 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
819 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
821 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
823 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
825 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
827 #define READ_REG(REG) ((REG)) argument
829 #define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) argument
/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/
A Dhal_pinctrl_iofunc.c58 #define _IOMUX_WRITE(REG, DATA, SHIFT, MASK) \ argument
61 HAL_DBG("PINCTRL Write before set reg val=0x%lx\n", REG); \
62 REG = ((DATA) << (SHIFT)) | ((MASK) << 16); \
63 HAL_DBG("PINCTRL Write after set reg val=0x%lx\n", REG); \
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g880f128.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g880f32.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g880f64.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f128.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f32.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f64.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Include/
A Defm32gg990f512.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32gg995f1024.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32gg995f512.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

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