Searched refs:REG32 (Results 1 – 25 of 31) sorted by relevance

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/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A D	gd32vf103_can.h	48 #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register … 49 #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ 50 #define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status r… 51 #define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 reg… 52 #define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 reg… 54 #define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ 55 #define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing regist… 77 #define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode regis… 78 #define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale regi… 315 #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) [all …]
A D	gd32vf103_dma.h	47 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ 50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control registe… 51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter registe… 55 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control registe… 56 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter registe… 60 #define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control registe… 61 #define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter registe… 65 #define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control registe… 66 #define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter registe… 70 #define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control registe… [all …]
A D	gd32vf103_rtc.h	45 #define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ 46 #define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ 47 #define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ 48 #define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ 49 #define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ 50 #define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ 51 #define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ 52 #define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ 53 #define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ 54 #define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
A D	gd32vf103_dac.h	47 #define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ 48 #define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ 49 #define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding re… 50 #define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding reg… 51 #define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding reg… 52 #define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding re… 53 #define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding reg… 54 #define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding reg… 56 #define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned d… 58 #define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ [all …]
A D	gd32vf103_adc.h	46 #define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ 47 #define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register … 48 #define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register … 49 #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time reg… 50 #define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time reg… 60 #define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence… 61 #define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data reg… 62 #define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data reg… 63 #define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data reg… 64 #define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data reg… [all …]
A D	gd32vf103_fmc.h	48 #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ 49 #define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ 50 #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key… 51 #define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ 52 #define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ 53 #define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ 54 #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status reg… 55 #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protectio… 56 #define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ 114 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) [all …]
A D	gd32vf103_i2c.h	46 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ 47 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ 48 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ 49 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ 50 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register … 51 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register … 52 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register … 53 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register … 54 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ 134 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) [all …]
A D	gd32vf103_exmc.h	46 #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash co… 47 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash ti… 48 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash wr… 94 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC… 95 #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC…
A D	gd32vf103_gpio.h	54 #define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ 55 #define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ 56 #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ 57 #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register… 58 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register … 59 #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ 60 #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock regi… 63 #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ 64 #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register … 65 #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection … [all …]
A D	gd32vf103_fwdgt.h	45 #define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control re… 46 #define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler … 47 #define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload reg… 48 #define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status reg…
A D	gd32vf103_timer.h	51 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control regis… 52 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… 55 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt fla… 57 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel contr… 58 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel contr… 59 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel contr… 60 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter regis… 61 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler reg… 62 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto … 63 #define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repet… [all …]
A D	gd32vf103_spi.h	47 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control re… 48 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control re… 49 #define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status reg… 50 #define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data regis… 51 #define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polyno… 52 #define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CR… 53 #define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit C… 54 #define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S contro… 55 #define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock …
A D	gd32vf103_crc.h	45 #define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ 46 #define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register … 47 #define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
A D	gd32vf103_wwdgt.h	45 #define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control re… 46 #define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configurat… 47 #define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status reg…
A D	gd32vf103_exti.h	45 #define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ 46 #define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ 47 #define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable regis… 48 #define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register … 49 #define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event registe… 50 #define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
A D	gd32vf103_usart.h	50 #define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register … 51 #define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ 52 #define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate regist… 53 #define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register… 54 #define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register… 55 #define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register… 56 #define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and p… 125 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)… 129 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
A D	gd32vf103_rcu.h	46 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ 47 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register… 48 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ 49 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ 50 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ 51 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ 52 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ 53 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ 55 #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock registe… 56 #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ [all …]
A D	gd32vf103_dbg.h	45 #define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ 46 #define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
A D	gd32vf103_pmu.h	45 #define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ 46 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register…
/bsp/sam7x/drivers/
A D	serial.c	28 typedef volatile rt_uint32_t REG32; typedef 31 REG32 US_CR; // Control Register 32 REG32 US_MR; // Mode Register 35 REG32 US_IMR; // Interrupt Mask Register 36 REG32 US_CSR; // Channel Status Register 42 REG32 Reserved0[5]; // 43 REG32 US_FIDI; // FI_DI_Ratio Register 44 REG32 US_NER; // Nb Errors Register 45 REG32 Reserved1[1]; // 46 REG32 US_IF; // IRDA_FILTER Register [all …]
/bsp/beaglebone/drivers/
A D	gpio.c	94 irqstatus = REG32(base + GPIO_IRQSTATUS(int_line)); in am33xx_gpio_hdr() 95 REG32(base + GPIO_IRQSTATUS(int_line)) = irqstatus; in am33xx_gpio_hdr() 207 REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber); in am33xx_pin_attach_irq() 210 REG32(baseAdd + GPIO_FALLINGDETECT) &= ~(1 << pinNumber); in am33xx_pin_attach_irq() 220 REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber); in am33xx_pin_attach_irq() 223 REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber); in am33xx_pin_attach_irq() 233 REG32(baseAdd + GPIO_RISINGDETECT) |= (1 << pinNumber); in am33xx_pin_attach_irq() 236 REG32(baseAdd + GPIO_FALLINGDETECT) |= (1 << pinNumber); in am33xx_pin_attach_irq() 249 REG32(baseAdd + GPIO_LEVELDETECT(1)) |= (1 << pinNumber); in am33xx_pin_attach_irq() 252 REG32(baseAdd + GPIO_RISINGDETECT) &= ~(1 << pinNumber); in am33xx_pin_attach_irq() [all …]
A D	uart.c	339 REG32(ctlm_base + 0x800 + 0x170) = 0x20; in config_pinmux() 340 REG32(ctlm_base + 0x800 + 0x174) = 0x00; in config_pinmux() 344 REG32(ctlm_base + 0x800 + 0x180) = 0x20; in config_pinmux() 345 REG32(ctlm_base + 0x800 + 0x184) = 0x00; in config_pinmux() 349 REG32(ctlm_base + 0x800 + 0x150) = 0x20; in config_pinmux() 350 REG32(ctlm_base + 0x800 + 0x154) = 0x00; in config_pinmux() 354 REG32(ctlm_base + 0x800 + 0x164) = 0x01; in config_pinmux() 358 REG32(ctlm_base + 0x800 + 0x070) = 0x26; in config_pinmux() 359 REG32(ctlm_base + 0x800 + 0x074) = 0x06; in config_pinmux() 363 REG32(ctlm_base + 0x800 + 0x0C4) = 0x24; in config_pinmux() [all …]
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/
A D	gd32vf103_eclic.c	116 REG32(REG_DBGMCU2EN) = (uint32_t)0x4b5a6978U; in eclic_system_reset() 117 REG32(REG_DBGMCU2) = (uint32_t)0x1U; in eclic_system_reset()
/bsp/nxp/lpc/lpc2148/drivers/
A D	serial.c	19 #define REG32(d) (*((volatile unsigned long *)(d))) macro 23 #define UART_IER(base) REG32(base + 0x04) 24 #define UART_IIR(base) REG32(base + 0x08) 33 #define UART_ACR(base) REG32(base + 0x20) 34 #define UART_FDR(base) REG32(base + 0x28)
/bsp/nxp/lpc/lpc2478/drivers/
A D	serial.c	19 #define REG32(d) (*((volatile unsigned long *)(d))) macro 23 #define UART_IER(base) REG32(base + 0x04) 24 #define UART_IIR(base) REG32(base + 0x08) 33 #define UART_ACR(base) REG32(base + 0x20) 34 #define UART_FDR(base) REG32(base + 0x28)

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Last Index update Fri Aug 22 02:45:11 CST 2025