1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __SOC_CTRL_H_
22 #define __SOC_CTRL_H_
23
24 //---------------------------------//
25 //
26 // Module: SOC_CTRL
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t info;
49 struct {
50 __IO uint32_t n_clusters : 16;
51 __IO uint32_t n_cores : 16;
52 } info_b;
53 };
54 __I uint32_t unused0[2];
55
56 // Offset = 0x000c
57 union {
58 __IO uint32_t build_date;
59 struct {
60 __IO uint32_t day : 8;
61 __IO uint32_t month : 8;
62 __IO uint32_t year : 16;
63 } build_date_b;
64 };
65
66 // Offset = 0x0010
67 union {
68 __IO uint32_t build_time;
69 struct {
70 __IO uint32_t seconds : 8;
71 __IO uint32_t minutes : 8;
72 __IO uint32_t hour : 8;
73 } build_time_b;
74 };
75 __I uint32_t unused1[24];
76
77 // Offset = 0x0074
78 union {
79 __IO uint32_t jtagreg;
80 };
81 __I uint32_t unused2[10];
82
83 // Offset = 0x00a0
84 union {
85 __IO uint32_t corestatus;
86 struct {
87 __IO uint32_t status : 31;
88 __IO uint32_t eoc : 1;
89 } corestatus_b;
90 };
91 __I uint32_t unused3[7];
92
93 // Offset = 0x00c0
94 union {
95 __IO uint32_t cs_ro;
96 struct {
97 __IO uint32_t status : 31;
98 __IO uint32_t eoc : 1;
99 } cs_ro_b;
100 };
101
102 // Offset = 0x00c4
103 union {
104 __IO uint32_t bootsel;
105 };
106
107 // Offset = 0x00c8
108 union {
109 __IO uint32_t clksel;
110 };
111 __I uint32_t unused4[3];
112
113 // Offset = 0x00d8
114 union {
115 __IO uint32_t clk_div_clu;
116 };
117 __I uint32_t unused5[1];
118
119 // Offset = 0x00e0
120 union {
121 __IO uint32_t sel_clk_dc_fifo_efpga;
122 };
123
124 // Offset = 0x00e4
125 union {
126 __IO uint32_t clk_gating_dc_fifo_efpga;
127 };
128
129 // Offset = 0x00e8
130 union {
131 __IO uint32_t reset_type1_efpga;
132 };
133
134 // Offset = 0x00ec
135 union {
136 __IO uint32_t enable_in_out_efpga;
137 };
138 __I uint32_t unused6[196];
139
140 // Offset = 0x0400
141 union {
142 __IO uint32_t io_ctrl[48];
143 struct {
144 __IO uint32_t mux : 2;
145 __IO uint32_t : 6;
146 __IO uint32_t cfg : 6;
147 } io_ctrl_b[48];
148 };
149 } SocCtrl_t;
150
151
152 #define REG_INFO 0x0000
153 #define REG_INFO_N_CORES_LSB 16
154 #define REG_INFO_N_CORES_MASK 0xffff
155 #define REG_INFO_N_CLUSTERS_LSB 0
156 #define REG_INFO_N_CLUSTERS_MASK 0xffff
157 #define REG_BUILD_DATE 0x000C
158 #define REG_BUILD_DATE_YEAR_LSB 16
159 #define REG_BUILD_DATE_YEAR_MASK 0xffff
160 #define REG_BUILD_DATE_MONTH_LSB 8
161 #define REG_BUILD_DATE_MONTH_MASK 0xff
162 #define REG_BUILD_DATE_DAY_LSB 0
163 #define REG_BUILD_DATE_DAY_MASK 0xff
164 #define REG_BUILD_TIME 0x0010
165 #define REG_BUILD_TIME_HOUR_LSB 16
166 #define REG_BUILD_TIME_HOUR_MASK 0xff
167 #define REG_BUILD_TIME_MINUTES_LSB 8
168 #define REG_BUILD_TIME_MINUTES_MASK 0xff
169 #define REG_BUILD_TIME_SECONDS_LSB 0
170 #define REG_BUILD_TIME_SECONDS_MASK 0xff
171 #define REG_JTAGREG 0x0074
172 #define REG_CORESTATUS 0x00A0
173 #define REG_CORESTATUS_EOC_LSB 31
174 #define REG_CORESTATUS_EOC_MASK 0x1
175 #define REG_CORESTATUS_STATUS_LSB 0
176 #define REG_CORESTATUS_STATUS_MASK 0x7fffffff
177 #define REG_CS_RO 0x00C0
178 #define REG_CS_RO_EOC_LSB 31
179 #define REG_CS_RO_EOC_MASK 0x1
180 #define REG_CS_RO_STATUS_LSB 0
181 #define REG_CS_RO_STATUS_MASK 0x7fffffff
182 #define REG_BOOTSEL 0x00C4
183 #define REG_CLKSEL 0x00C8
184 #define REG_CLK_DIV_CLU 0x00D8
185 #define REG_SEL_CLK_DC_FIFO_EFPGA 0x00E0
186 #define REG_CLK_GATING_DC_FIFO_EFPGA 0x00E4
187 #define REG_RESET_TYPE1_EFPGA 0x00E8
188 #define REG_ENABLE_IN_OUT_EFPGA 0x00EC
189 #define REG_IO_CTRL 0x0400
190 #define REG_IO_CTRL_CFG_LSB 8
191 #define REG_IO_CTRL_CFG_MASK 0x3f
192 #define REG_IO_CTRL_MUX_LSB 0
193 #define REG_IO_CTRL_MUX_MASK 0x3
194
195 #ifndef __REGFIELD_OPS_
196 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)197 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
198 return (reg >> lsb) & mask;
199 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)200 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
201 reg &= ~(mask << lsb);
202 reg |= (value & mask) << lsb;
203 return reg;
204 }
205 #endif // __REGFIELD_OPS_
206
207 #endif // __SOC_CTRL_H_
208