1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __APB_GPIO_H_
22 #define __APB_GPIO_H_
23
24 //---------------------------------//
25 //
26 // Module: APB_GPIO
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t setgpio;
49 struct {
50 __IO uint32_t gpio_num : 8;
51 } setgpio_b;
52 };
53
54 // Offset = 0x0004
55 union {
56 __IO uint32_t clrgpio;
57 struct {
58 __IO uint32_t gpio_num : 8;
59 } clrgpio_b;
60 };
61
62 // Offset = 0x0008
63 union {
64 __IO uint32_t toggpio;
65 struct {
66 __IO uint32_t gpio_num : 8;
67 } toggpio_b;
68 };
69 __I uint32_t unused0[1];
70
71 // Offset = 0x0010
72 union {
73 __IO uint32_t pin0;
74 struct {
75 __IO uint32_t gpio_value : 32;
76 } pin0_b;
77 };
78
79 // Offset = 0x0014
80 union {
81 __IO uint32_t pin1;
82 struct {
83 __IO uint32_t gpio_value : 32;
84 } pin1_b;
85 };
86
87 // Offset = 0x0018
88 union {
89 __IO uint32_t pin2;
90 struct {
91 __IO uint32_t gpio_value : 32;
92 } pin2_b;
93 };
94
95 // Offset = 0x001c
96 union {
97 __IO uint32_t pin3;
98 struct {
99 __IO uint32_t gpio_value : 32;
100 } pin3_b;
101 };
102
103 // Offset = 0x0020
104 union {
105 __IO uint32_t out0;
106 struct {
107 __IO uint32_t value : 32;
108 } out0_b;
109 };
110
111 // Offset = 0x0024
112 union {
113 __IO uint32_t out1;
114 struct {
115 __IO uint32_t value : 32;
116 } out1_b;
117 };
118
119 // Offset = 0x0028
120 union {
121 __IO uint32_t out2;
122 struct {
123 __IO uint32_t value : 32;
124 } out2_b;
125 };
126
127 // Offset = 0x002c
128 union {
129 __IO uint32_t out3;
130 struct {
131 __IO uint32_t value : 32;
132 } out3_b;
133 };
134
135 // Offset = 0x0030
136 union {
137 __IO uint32_t setsel;
138 struct {
139 __IO uint32_t gpio_num : 8;
140 } setsel_b;
141 };
142
143 // Offset = 0x0034
144 union {
145 __IO uint32_t rdstat;
146 struct {
147 __IO uint32_t gpio_sel : 8;
148 __IO uint32_t output : 1;
149 __IO uint32_t : 3;
150 __IO uint32_t input : 1;
151 __IO uint32_t : 3;
152 __IO uint32_t inten : 1;
153 __IO uint32_t inttype : 3;
154 __IO uint32_t : 4;
155 __IO uint32_t mode : 2;
156 } rdstat_b;
157 };
158
159 // Offset = 0x0038
160 union {
161 __IO uint32_t setmode;
162 struct {
163 __IO uint32_t gpio_num : 8;
164 __IO uint32_t : 16;
165 __IO uint32_t mode : 2;
166 } setmode_b;
167 };
168
169 // Offset = 0x003c
170 union {
171 __IO uint32_t setint;
172 struct {
173 __IO uint32_t gpio_num : 8;
174 __IO uint32_t : 8;
175 __IO uint32_t intenable : 1;
176 __IO uint32_t inttype : 3;
177 } setint_b;
178 };
179 union {
180 __IO uint32_t intack;
181 struct {
182 __IO uint32_t gpio_num : 8;
183 __IO uint32_t : 24;
184 } intack_b;
185 };
186 } ApbGpio_t;
187
188
189 #define REG_SETGPIO 0x00
190 #define REG_SETGPIO_gpio_num_LSB 0
191 #define REG_SETGPIO_gpio_num_MASK 0xff
192 #define REG_CLRGPIO 0x04
193 #define REG_CLRGPIO_gpio_num_LSB 0
194 #define REG_CLRGPIO_gpio_num_MASK 0xff
195 #define REG_TOGGPIO 0x08
196 #define REG_TOGGPIO_gpio_num_LSB 0
197 #define REG_TOGGPIO_gpio_num_MASK 0xff
198 #define REG_PIN0 0x10
199 #define REG_PIN0_gpio_value_LSB 0
200 #define REG_PIN0_gpio_value_MASK 0xffffffff
201 #define REG_PIN1 0x14
202 #define REG_PIN1_gpio_value_LSB 0
203 #define REG_PIN1_gpio_value_MASK 0xffffffff
204 #define REG_PIN2 0x18
205 #define REG_PIN2_gpio_value_LSB 0
206 #define REG_PIN2_gpio_value_MASK 0xffffffff
207 #define REG_PIN3 0x1C
208 #define REG_PIN3_gpio_value_LSB 0
209 #define REG_PIN3_gpio_value_MASK 0xffffffff
210 #define REG_OUT0 0x20
211 #define REG_OUT0_value_LSB 0
212 #define REG_OUT0_value_MASK 0xffffffff
213 #define REG_OUT1 0x24
214 #define REG_OUT1_value_LSB 0
215 #define REG_OUT1_value_MASK 0xffffffff
216 #define REG_OUT2 0x28
217 #define REG_OUT2_value_LSB 0
218 #define REG_OUT2_value_MASK 0xffffffff
219 #define REG_OUT3 0x2C
220 #define REG_OUT3_value_LSB 0
221 #define REG_OUT3_value_MASK 0xffffffff
222 #define REG_SETSEL 0x30
223 #define REG_SETSEL_gpio_num_LSB 0
224 #define REG_SETSEL_gpio_num_MASK 0xff
225 #define REG_RDSTAT 0x34
226 #define REG_RDSTAT_mode_LSB 24
227 #define REG_RDSTAT_mode_MASK 0x3
228 #define REG_RDSTAT_INTTYPE_LSB 16
229 #define REG_RDSTAT_INTTYPE_MASK 0x7
230 #define REG_RDSTAT_INPUT_LSB 12
231 #define REG_RDSTAT_INPUT_MASK 0x1
232 #define REG_RDSTAT_OUTPUT_LSB 8
233 #define REG_RDSTAT_OUTPUT_MASK 0x1
234 #define REG_SETMODE 0x38
235 #define REG_SETMODE_mode_LSB 24
236 #define REG_SETMODE_mode_MASK 0x3
237 #define REG_SETMODE_gpio_num_LSB 0
238 #define REG_SETMODE_gpio_num_MASK 0xff
239 #define REG_SETINT 0x3C
240 #define REG_SETINT_INTTYPE_LSB 17
241 #define REG_SETINT_INTTYPE_MASK 0x7
242 #define REG_SETINT_INTENABLE_LSB 16
243 #define REG_SETINT_INTENABLE_MASK 0x1
244 #define REG_SETINT_gpio_num_LSB 0
245 #define REG_SETINT_gpio_num_MASK 0xff
246
247 #ifndef __REGFIELD_OPS_
248 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)249 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
250 return (reg >> lsb) & mask;
251 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)252 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
253 reg &= ~(mask << lsb);
254 reg |= (value & mask) << lsb;
255 return reg;
256 }
257 #endif // __REGFIELD_OPS_
258
259 #endif // __APB_GPIO_H_
260