| /bsp/yichip/yc3121-pos/drivers/linker_scripts/ |
| A D | link.sct | 8 ; startup.o (.text,+RO)
15 flash_start.o (|.flash_start|,+RO)
18 startup.o (|.INIT_STACK_HEAP|,+RO)
25 .ANY (+RO)
|
| /bsp/rx/ |
| A D | project.vpwhist | 32 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
35 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
38 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
41 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
44 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
47 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
50 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
53 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
56 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
59 BI: MA=1 74 1 TABS=1 5 WWS=1 IWT=0 ST=8 IN=2 BW=0 US=32000 RO=0 SE=1 SN=0 BIN=0 MN=C/C++ HM=0 MF=…
[all …]
|
| /bsp/nxp/mcx/mcxn/frdm-mcxn947/board/linker_scripts/ |
| A D | MCXN947_cm33_core0_flash.scf | 89 .ANY (+RO)
103 ; // lv_draw*.o (+RO +ZI +RW)
104 ; // lv_img*.o (+RO +ZI +RW)
|
| /bsp/Vango/v85xx/ |
| A D | Target_FLASH.sct | 9 .ANY (+RO)
13 lib_CodeRAM.o (+RO +ZI +RW)
|
| /bsp/fujitsu/mb9x/mb9bf568r/ |
| A D | rtthread-mb9bf568r.sct | 9 .ANY (+RO)
21 .ANY (+RO)
|
| /bsp/airm2m/air105/libraries/HAL_Driver/Inc/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/samc21/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/saml10/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/same70/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/stm32/libraries/HAL_Drivers/CMSIS/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/yichip/yc3122-pos/Libraries/CMSIS/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/microchip/same54/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/essemi/es32f369x/libraries/CMSIS/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/airm2m/air105/libraries/HAL_Driver/Src/ |
| A D | core_otp.c | 31 OTP->RO = 0; in OTP_Write()
58 OTP->RO = 0xffffffff; in OTP_Lock()
|
| /bsp/acm32/acm32f4xx-nucleo/libraries/CMSIS/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/tae32f5300/Libraries/CMSIS/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 80 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) argument
89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|