1 /* 2 * Copyright (c) 2006-2021, JuiceVm Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021/04/22 Juice the first version 9 */ 10 #ifndef __RV_MTVEC_MAP_H__ 11 #define __RV_MTVEC_MAP_H__ 12 #include "rv_config.h" 13 14 #define rv_sim_pdev_base_addr (RV_CPU_SIM_RAM_START_ADDR+RV_CPU_SIM_RAM_SIZE) 15 #define rv_sim_pdev_uart0_base_addr (rv_sim_pdev_base_addr) 16 #define pdev_uart0_write_addr (rv_sim_pdev_uart0_base_addr) 17 #define pdev_uart0_read_addr (rv_sim_pdev_uart0_base_addr+1) 18 #define pdev_uart0_free_state 0x00 19 #define pdev_uart0_readbusy_state 0x01 20 #define pdev_uart0_state_addr (rv_sim_pdev_uart0_base_addr+2) 21 22 #define rv_sim_pdev_mtime_base_addr (rv_sim_pdev_base_addr+3) 23 #define pdev_mtime_mtime_addr (rv_sim_pdev_mtime_base_addr) 24 #define pdev_mtime_mtimecmp_addr (rv_sim_pdev_mtime_base_addr+4) 25 26 #define uart0_irq_flag 0 27 #define uart0_irq_ecode 24 28 29 #define RV_exception_Instruction_address_misaligned_IFLAG 0 30 #define RV_exception_Instruction_address_misaligned_ECODE 0 31 #define RV_exception_Instruction_access_fault_IFLAG 0 32 #define RV_exception_Instruction_access_fault_ECODE 1 33 #define RV_exception_Illegal_Instruction_IFLAG 0 34 #define RV_exception_Illegal_Instruction_ECODE 2 35 #define RV_exception_Breakpoint_IFLAG 0 36 #define RV_exception_Breakpoint_ECODE 3 37 #define RV_exception_LoadAddress_Misaligned_IFLAG 0 38 #define RV_exception_LoadAddress_Misaligned_ECODE 4 39 #define RV_exception_Load_access_fault_IFLAG 0 40 #define RV_exception_Load_access_fault_ECODE 5 41 42 #define RV_exception_Store_or_AMO_Address_Misaligned_IFLAG 0 43 #define RV_exception_Store_or_AMO_Address_Misaligned_ECODE 6 44 45 #define RV_exception_Store_or_AMO_access_fault_IFLAG 0 46 #define RV_exception_Store_or_AMO_access_fault_ECODE 7 47 48 #define RV_exception_Environment_call_from_Umode_IFLAG 0 49 #define RV_exception_Environment_call_from_Umode_ECODE 8 50 51 #define RV_exception_Environment_call_from_Smode_IFLAG 0 52 #define RV_exception_Environment_call_from_Smode_ECODE 9 53 54 #define RV_exception_Environment_Call_FromMachine_IFLAG 0 55 #define RV_exception_Environment_Call_FromMachine_ECODE 11 56 57 #define RV_exception_FloatingPoint_Disabled_IFLAG 58 #define RV_exception_FloatingPoint_Disabled_ECODE 59 60 #define RV_exception_Instruction_page_fault_IFLAG 0 61 #define RV_exception_Instruction_page_fault_ECODE 12 62 #define RV_exception_Load_page_fault_IFLAG 0 63 #define RV_exception_Load_page_fault_ECODE 13 64 65 #define RV_exception_Store_or_AMO_page_fault_IFLAG 0 66 #define RV_exception_Store_or_AMO_page_fault_ECODE 15 67 68 69 // Interrupt Exception Code Description 70 // 1 0 Reserved 71 // 1 1 Supervisor software interrupt not support 72 // 1 2 Reserved 73 // 1 3 Machine software interrupt not support 74 // 1 4 Reserved 75 // 1 5 Supervisor timer interrupt not support 76 // 1 6 Reserved 77 // 1 7 Machine timer interrupt support 78 // 1 8 Reserved 79 // 1 9 Supervisor external interrupt not support 80 // 1 10 Reserved 81 // 1 11 Machine external interrupt not support 82 // 1 12 Reserved 83 // 1 13 Reserved 84 // 1 14 Reserved 85 // 1 15 Reserved 86 // // 1 ≥16 Designated for platform use 87 // 0 0 Instruction address misaligned not support 88 // 0 1 Instruction access fault not support 89 // 0 2 Illegal instruction support 90 // 0 3 Breakpoint support 91 // 0 4 Load address misaligned support 92 // 0 5 Load access fault not support 93 // 0 6 Store/AMO address misaligned support 94 // 0 7 Store/AMO access fault not support 95 // 0 8 Environment call from U-mode not support 96 // 0 9 Environment call from S-mode not support 97 // 0 10 Reserved 98 // 0 11 Environment call from M-mode support 99 // 0 12 Instruction page fault not support 100 // 0 13 Load page fault not support 101 // 0 14 Reserved 102 // 0 15 Store/AMO page fault not support 103 // 0 16-23 Reserved 104 // // 0 24–31 Designated for custom use 105 // 0 32-47 Reserved 106 // // 0 48–63 Designated for custom use 107 // 0 ≥64 Reserved 108 109 110 // #define mtime_irq_flag 1 111 // #define mtime_irq_ecode 7 112 113 #define RV_Supervisor_software_interrupt_IFLAG 1 114 #define RV_Supervisor_software_interrupt_ECODE 1 115 116 #define RV_Machine_software_interrupt_IFLAG 1 117 #define RV_Machine_software_interrupt_ECODE 3 118 119 #define RV_Supervisor_timer_interrupt_IFLAG 1 120 #define RV_Supervisor_timer_interrupt_ECODE 5 121 122 #define RV_Machine_timer_interrupt_IFLAG 1 123 #define RV_Machine_timer_interrupt_ECODE 7 124 125 #define RV_Supervisor_external_interrupt_IFLAG 1 126 #define RV_Supervisor_external_interrupt_ECODE 9 127 128 #define RV_Machine_external_interrupt_IFLAG 1 129 #define RV_Machine_external_interrupt_ECODE 10 130 131 #endif // __RV_MTVEC_MAP_H__ 132