Searched refs:RegVal (Results 1 – 5 of 5) sorted by relevance
| /bsp/ft2004/libraries/bsp/ft_gpio/ |
| A D | ft_gpio.c | 25 u32 RegVal; in FGpio_SetGroupModeA() local
33 RegVal &= ~(1 << pin); in FGpio_SetGroupModeA()
36 RegVal |= (1 << pin); in FGpio_SetGroupModeA()
49 u32 RegVal; in FGpio_SetPinInOutA() local
54 if (inOut != (RegVal & (0x1 << pin))) in FGpio_SetPinInOutA()
58 RegVal &= ~(0x1 << pin); in FGpio_SetPinInOutA()
62 RegVal |= (0x1 << pin); in FGpio_SetPinInOutA()
77 u32 RegVal; in FGpio_ReadPinA() local
90 u32 RegVal; in FGpio_WritePinA() local
99 RegVal &= ~(1 << pin); in FGpio_WritePinA()
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| /bsp/ft2004/libraries/bsp/ft_i2c/ |
| A D | ft_i2c_irq.c | 20 u32 RegVal; in FI2C_irqHandler() local
26 RegVal = FI2C_GET_IRQ_STATUS(pDev); in FI2C_irqHandler()
27 if (I2C_IRQ_RX_FULL & RegVal) in FI2C_irqHandler()
31 else if (I2C_IRQ_TX_EMPTY & RegVal) in FI2C_irqHandler()
57 u32 RegVal; in FI2C_irqHandler4Fifo() local
80 if (I2C_IRQ_RX_FULL & RegVal) in FI2C_irqHandler4Fifo()
136 u32 RegVal; in FI2C_getIrqMask() local
140 return RegVal; in FI2C_getIrqMask()
145 u32 RegVal; in FI2C_setIrqMask() local
149 FI2C_SET_IRQ_MASK(pDev, RegVal); in FI2C_setIrqMask()
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| A D | ft_i2c.c | 86 u32 RegVal; in FI2C_setCtrlParam() local
92 FI2C_WriteReg(BaseAddr, I2C_CON, RegVal); in FI2C_setCtrlParam()
207 u32 RegVal = FI2C_ReadReg(BaseAddr, I2C_CON); in FI2C_sendRestartCmd() local
208 RegVal |= I2C_CON_RESTART_EN; in FI2C_sendRestartCmd()
209 FI2C_WriteReg(BaseAddr, I2C_CON, RegVal); in FI2C_sendRestartCmd()
214 u32 RegVal = (SlaveAddr & I2C_TAR_ADR_MASK); in FI2C_setTarAddr() local
215 FI2C_WriteReg(BaseAddr, I2C_TAR, RegVal); in FI2C_setTarAddr()
221 FI2C_WriteReg(BaseAddr, I2C_DATA_CMD, RegVal); in FI2C_sendWriteCmd()
228 FI2C_WriteReg(BaseAddr, I2C_DATA_CMD, RegVal); in FI2C_sendStartReadCmd()
234 u32 RegVal = I2C_DATA_CMD_STOP; in FI2C_sendStopCmd() local
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| /bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/ |
| A D | xemacps_hw.c | 63 u32 RegVal; in XEmacPs_ResetHw() local
69 RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET); in XEmacPs_ResetHw()
70 RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK| in XEmacPs_ResetHw()
75 RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK| in XEmacPs_ResetHw()
77 XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal); in XEmacPs_ResetHw()
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| /bsp/rm48x50/HALCoGen/include/ |
| A D | mdio.h | 36 uint32 regNum, uint16 RegVal);
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